Jayaprakash Balachandran

Characterisation, modelling and design of bond-wire interconnects for chip-package co-design

This work is a comprehensive experimental investigation of chip to package wirebond interconnects for chip-package co-design. Wirebonds are interconnect bottlenecks in RF design, but are difficult to avoid due to their low cost and manufacturing ease. We have shown measurements on wirebonds in coplanar configuration with different return paths and also the cross coupling. We have also extracted lumped and distributed models and demonstrate the excellent agreement with measurements atleast upto 15GHz. We have proposed multi-wirebonds as a potential solution for better impedance matching. Different types of inductors with Q-factors of upto 100 have also been illustrated. We show influence of encapsulant on wirebonds and finally we also demonstrate a methodology to extract the time-domain response from S-parameters.

Package level interconnect options

Scaling enhances intrinsic transistor performance and degrades interconnects. As the technology steps into nanometer era, global interconnects are becoming bottleneck for overall chip performance. In this paper, we show package level interconnects are an effective alternative for on-chip global wiring. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance - bandwidth, bandwidth density, latency and power consumption - of the package level transmission lines with conventional on-chip global interconnects for different ITRS technology nodes. Based on these results, we show package level interconnects are well suited for power demanding low latency applications and we analyze different interconnect options like memory buses, long inter tile interconnects, clock and power distribution.

Extending on-die wiring hierarchy with wafer level packaging concepts

Wafer level package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.

Compact broadband resistance model for microstrip transmission lines

This work presents a closed form broadband resistance model for microstrip transmission lines. The proposed model is compact and scalable, and is within 7% of experimental values. The model uses a non-discontinuous analytical function valid in all bands ranging from DC to microwave frequencies.

Constant Impedance Scaling Paradigm for Scaling LC transmission lines

Reverse scaled LC transmission lines are an effective alternative to on-chip global interconnects which severely limit the chip performance in nano-CMOS technologies. However, the main disadvantage of the LC transmission line approach is their poor wiring density. The scaling of LC transmission lines is formally analyzed with the proposed constant impedance scaling paradigm that simultaneously maximize performance and wiring density. With this paradigm, we show that the LC transmission line implementation would need a minimum pitch of 8mum for line lengths in the range of 10 to 20 mm, considering a low-k dielectric of relative dielectric constant of 2.7

Efficient Link Architecture for On-Chip Serial links and Networks

Serial links are an effective solution to address the growing on-chip communication bottlenecks in nano-CMOS technologies. This paper proposes efficient link architecture for on-chip serial links and networks. The proposed solution consists of a pre-emphasized differential driver and receiver interconnected by LC transmission lines. The LC transmission lines are implemented in packaging layers post processed directly above a standard CMOS wafer. The link enables simple register-to-register style data transfer, well suited for on-chip IO. The proposed scheme can offer data rates as high as 12.5 Gbps per channel for less than 0.5pJ of energy per bit on the 0.13mum technology

Analysis and Modeling of Power Grid Transmission lines

Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission lines in power grids. The transmission lines are well suited for high quality intra-chip signal transmission at multi gigabit data rates. By having signal lines between the power grids, the VDD and GND lines in the grid can be exploited as return paths besides being used for regular power distribution. This approach also improves wiring density. In this paper, we rigorously analyze and discuss the design considerations for laying transmission lines in power grids. We also present design oriented modeling methods in 2D and 3D geometry. We show how the grid modeling complexity is simplified. We experimentally validate our results with fabricated test structures. We also show VDD lines in the grid act as good return path without external decoupling capacitors in our design. Further we discuss substrate effects and deduce guidelines for designing power grid transmission lines on a low resistive silicon substrate

Constant impedance scaling paradigm for interconnect synthesis

On-chip global interconnects perceived as performance limiters for continued scaling of integrated circuits in nano-CMOS regimes highlight the importance of their proper design and optimization. A constant impedance scaling paradigm is proposed for systematic synthesis of complete interconnects physical parameters from system level performance metrics such as delay, power and wiring density. The methodology is illustrated for different system level targets and optimal physical parameters are deduced.

Accurate broadband parameter extraction methodology for S-parameter measurements

GHz range operating frequencies of todays semiconductor devices demand accurate interconnect models. Constructing accurate and scalable models require extraction of interconnect parameters namely resistance-R, inductance-L, capacitance-C and conductance-G from measured S-parameters. The parameter extraction is error prone influenced by half-wavelength resonance. In this paper, we present a new methodology for accurately extracting interconnect parameters from measured S-parameters. We first analyze the parameter extraction errors and show that it can be mainly attributed to non-perfect de-embedding. Based on the error analysis, we derive an extraction flow for accurate interconnect characterization. The proposed method is validated with fabricated transmission line test structures. Extracted line parameters agree with well-known theoretical models, establishing accuracy of the method.