Jean-François Boland

A methodology for system-level fault injection based on gate-level faulty behavior

In this paper a methodology for creating a high-level faulty models library for simulating low-level fault injection is proposed. The concept of faulty behavior Signature is first proposed in this work. This paper demonstrates how faulty behavior Signatures allow building high level models, for example using Simulink, that reflect with high fidelity the faulty behavior of a combinational circuit represented at gate-level injected with one fault arbitrarily selected from a fault list. It is shown that we are able to capture this behavior with a correlation coefficient of 99.93%.

Multi-abstraction level signature generation and comparison based on radiation single event upset

Whereas the use of FPGAs in aerospace applications is increasing, concerns about its sensitivity to radiations more particularly the single event upsets (SEU) in SRAM-based FPGA is enhanced as well. To ensure hardness assurance, radiation sensitivity should be estimated at different stages of the system development cycle. In this paper, we present a multi-abstraction level signature generation based on fault injection using fault simulation, fault emulation and radiation testing in order to build an accurate representation of the design faulty behavior. These signatures, which can be seen as high-level fault models, help the designer make decisions on the use (or not) of rad-hard components and the adequate mitigation technique very early in the design process. Results from the different types of signatures are compared. It first shows that the type of resources used to implement a module (e.g. multiplier) may influence its behavior when affected by an SEU. It also reveals that most of the faulty values observed during radiation testing appear in the simulation-based and emulation-based signatures, but that their frequency of occurrence can differ. Finally, limitations of some commercial tools to identify critical bits are investigated.

Fault tolerant flight control system using emmae method and reconfiguration with sliding mode technique

This paper presents a fault tolerant flight control system. The Extended Multiple Model Adaptive Estimation EMMAE method is used to design the Fault Detection and Diagnosis FDD process. This process is able to detect, isolate and identify in real time faults that occurs in aircraft actuator. Based on information given by FDD process, a Sliding Mode Controller (SMC) is designed to compensate effects of such faults, and allows the aircraft to accomplish its mission safety with acceptable performances.

A novel low-overhead flexible instrumentation framework for virtual platforms

Instrumentation methods for code profiling, tracing and semihosting on virtual platforms (VP) and instruction-set simulators (ISS) rely on function call and system call interception. To reduce instrumentation overhead that can affect program behavior and timing, we propose a novel low-overhead flexible instrumentation framework called Virtual Platform Instrumentation (VPI). The VPI framework uses a new table-based parameter-passing method that reduces the runtime overhead of instrumentation to only that of the interception. Furthermore, it provides a high-level interface to extend the functionality of any VP or ISS with debugging support, without changes to their source code. Our framework unifies the implementation of tracing, profiling and semihosting use cases, while at the same time reducing detrimental runtime overhead on the target as much as 90% compared to widely deployed traditional methods, without significant simulation time penalty.

Automatic verification methodology based on structural test patterns

Functional verification is a major bottleneck in todays design flow. Current technologies are not meeting the challenges imposed by design complexity. In this paper, we propose a new simulation-based verification methodology based on the use of automatically generated structural test patterns in the RTL simulation. The presented approach generally improves the simulation-based verifications quality, keeping the integration, the applicability and the automation aspects in close proximity.

Use of structural tests in RTL verification

Functional verification is a major hurdle in todaypsilas design flow. Current technologies are not meeting the challenges imposed by design complexity. Dark corners detection is still the simulation bottleneck in the verification process. While functional verification remains not sufficiently mature, test techniques are improved and completely automated, accordingly complex circuits can be tested in few seconds and hard faults can be covered with no effort. In this paper, we establish the relationship existing between dark corners and hard faults. Based on this relation, we explore the use of structural test patterns in the verification process and compare the results to well-known verification techniques.

An efficient methodology for design and verification of an equalizer for a software defined radio

Design and verification of integrated systems involve a variety of CAD tools, which increase design heterogeneity. This paper presents an efficient methodology based on tool integration that regulates the design and verification flow. The methodology aims at solving key issues in building and verifying a functional prototype of a system and in improving design continuity. Using UML, SystemC and Matlab/Simulink, we were able to create a unified design and verification framework. A digital equalizer is used as an example to validate the methodology.

Functional Constraint Extraction From Register Transfer Level for ATPG

The use of scan test patterns, generated at the gate level with automatic test pattern generation (ATPG) tools in design simulation, was proposed in our previous work to improve verification quality. A drawback of this method is the potential presence of illegal (or unreachable) states (ISEs) causing unwanted behavior and false error detection in the verification process. In this brief, we present a new automated tool that helps overcome this problem. The tool extracts functional constraints at the register transfer level on a VHDL description (it can be easily adapted to any other hardware description language). The constraints extracted are used in the ATPG process to generate pseudofunctional scan test patterns which avoid the ISEs. The whole verification environment incorporating the proposed tool is presented. Experimental results show the tool impact on the reduction of false error detection in verification. In addition, it shows the verification quality improvements with the proposed environment in terms of coverage, time, and complexity.

Illegal state extraction from Register Transfer Level

In this paper we present a new automated tool for illegal state identification at Register Transfer Level (RTL). This tool is the cornerstone of a new methodology for functional constraints extraction, to be applied in the ATPG process. Results show that our tool helps reducing overtesting and false error detection during verification.

Modeling the faulty behaviour of digital designs using a feed forward neural network approach

Cosmic rays lead to soft errors and faulty behavior in electronic circuits. Knowing about their faulty behavior before fabrication would be helpful. This research proposes an approach for modeling the faulty behaviour of digital circuits. It could be applied in a design flow before circuit fabrication. This is achieved by extracting information about faulty behaviour of circuits from low-level models expressed in the VHDL language. Afterwards the extracted information is used to train high-level artificial neural networks models expressed in C/C++ or MATLABTM languages. The trained neural network models are able to replicate the behaviour of circuits in presence of faults. The methodology is based on experiments done with two benchmarks, the ISCAS-C17 and a 4-bit multiplier. Results show that the neural network approach leads to models that are more accurate than a previously reported signature generation method. For the C17, using only 30% of the dataset generated with the LIFTING fault simulator, the neural network is able to replicate the output of the circuit in presence of faults with a mean absolute modeling error below 6%.