Christelle Hobeika

Multi-abstraction level signature generation and comparison based on radiation single event upset

Whereas the use of FPGAs in aerospace applications is increasing, concerns about its sensitivity to radiations more particularly the single event upsets (SEU) in SRAM-based FPGA is enhanced as well. To ensure hardness assurance, radiation sensitivity should be estimated at different stages of the system development cycle. In this paper, we present a multi-abstraction level signature generation based on fault injection using fault simulation, fault emulation and radiation testing in order to build an accurate representation of the design faulty behavior. These signatures, which can be seen as high-level fault models, help the designer make decisions on the use (or not) of rad-hard components and the adequate mitigation technique very early in the design process. Results from the different types of signatures are compared. It first shows that the type of resources used to implement a module (e.g. multiplier) may influence its behavior when affected by an SEU. It also reveals that most of the faulty values observed during radiation testing appear in the simulation-based and emulation-based signatures, but that their frequency of occurrence can differ. Finally, limitations of some commercial tools to identify critical bits are investigated.

Automatic verification methodology based on structural test patterns

Functional verification is a major bottleneck in todays design flow. Current technologies are not meeting the challenges imposed by design complexity. In this paper, we propose a new simulation-based verification methodology based on the use of automatically generated structural test patterns in the RTL simulation. The presented approach generally improves the simulation-based verifications quality, keeping the integration, the applicability and the automation aspects in close proximity.

Use of structural tests in RTL verification

Functional verification is a major hurdle in todaypsilas design flow. Current technologies are not meeting the challenges imposed by design complexity. Dark corners detection is still the simulation bottleneck in the verification process. While functional verification remains not sufficiently mature, test techniques are improved and completely automated, accordingly complex circuits can be tested in few seconds and hard faults can be covered with no effort. In this paper, we establish the relationship existing between dark corners and hard faults. Based on this relation, we explore the use of structural test patterns in the verification process and compare the results to well-known verification techniques.

Functional Constraint Extraction From Register Transfer Level for ATPG

The use of scan test patterns, generated at the gate level with automatic test pattern generation (ATPG) tools in design simulation, was proposed in our previous work to improve verification quality. A drawback of this method is the potential presence of illegal (or unreachable) states (ISEs) causing unwanted behavior and false error detection in the verification process. In this brief, we present a new automated tool that helps overcome this problem. The tool extracts functional constraints at the register transfer level on a VHDL description (it can be easily adapted to any other hardware description language). The constraints extracted are used in the ATPG process to generate pseudofunctional scan test patterns which avoid the ISEs. The whole verification environment incorporating the proposed tool is presented. Experimental results show the tool impact on the reduction of false error detection in verification. In addition, it shows the verification quality improvements with the proposed environment in terms of coverage, time, and complexity.

Illegal state extraction from Register Transfer Level

In this paper we present a new automated tool for illegal state identification at Register Transfer Level (RTL). This tool is the cornerstone of a new methodology for functional constraints extraction, to be applied in the ATPG process. Results show that our tool helps reducing overtesting and false error detection during verification.

On Captureless Delay Test Points

In this paper we present a new technique called Captureless Delay Testing Points (CDTP). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The CDTP random patterns are internally generated, requiring virtually no additional test time or memory tester. Area/performance overhead and technical obstacles to automation are minimal. Results show that CDTP provides appreciable coverage increase with minimum overhead.

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.