Jean-Francois Carpentier

A SiGe:C BiCMOS WCDMA zero-IF RF front-end using an above-IC BAW filter

The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a voltage gain of 31.3dB, a noise figure of 5.3dB, an in-band IIP3 of -8dBm and IIP2 of 38dBm, with a total power consumption of 36mW. The BAW filter area is 0.45mm/sup 2/ and the total circuit area including the BAW filter is 2.44mm/sup 2/.

Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process

Capacitive measurement of very small displacement of nano-electro-mechanical systems (NEMS) presents some issues that are discussed in this article. It is shown that performance is fairly improved when integrating on a same die the NEMS and CMOS electronics. As an initial step toward full integration, an in-plane suspended gate MOSFET (SGMOSFET) compatible with a front-end CMOS has been developed. The device model, its fabrication, and its experimental measurement are presented. Performance obtained with this device is experimentally compared to the one obtained with a stand-alone NEMS readout circuit, which is used as a reference detection system. The 130 nm CMOS ASIC uses a bridge measurement technique and a high sensitive first stage to minimize the influence of any parasitic capacitances.

A tunable bandpass BAW-filter architecture and its application to WCDMA filter

We present a tunable bandpass BAW-filter based in a first step on a hybrid integration concept to demonstrate the validity of our architecture and to evaluate the potential of such filters. The filter consists of two cascaded lattices incorporating four BAW resonators, coupled with high-Q inductors and wide tuning range active varactors. The simulated results show that it is possible to compensate ′1% deviation on the filter center frequency. The prototype is currently in manufacturing and the experimental results will be available for the conference.

Band Reject Filter in BAW Technology

This document shows the feasibility of a band reject filter in Bulk Acoustic Wave (BAW) technology. This type of filter is usually composed of series and shunt resonators. We present two setups centred at 2.5 GHz which measurement is agreed with simulation for rejection band. Filters give a -20 dB rejection on a bandwidth greater than 60 MHz for each topology. The best measured filter achieves a -1.4 dB insertion loss in the passband with a 200 MHz bandwidth.

60μW SMR BAW oscillator designed in 65nm CMOS technology

This paper presents the simulation results of a BAW- based low power oscillator. The oscillator was designed using high-Q solidly mounted bulk acoustic wave resonators (SMR BAW) exhibiting quality factor around 2200. The oscillator is simulated using RF transistors of the CMOS 65 nm process from STMicroelectronics. The oscillator was optimized for low power purpose and consumes 50 muA from a 1.2 V source with phase noise performance of -124 dBc/Hz at 100 KHz offset. The impact of the bias current on phase noise, output voltage and oscillation frequency was also studied.

Linear Transmitter Architecture Using BAW Filter

A bulk acoustic wave filter, which can be used in EDGE transmitter, is presented in this paper. It attenuates power amplifier harmonic frequencies and out-of-band noise generated by sigma-delta modulator needed in linear architecture. This filter achieves 2.4 dB insertion loss including matching network to 50 Omega and more than 15 dB of return loss. Power handling capability and linearity performance of bulk acoustic wave devices are detailed and satisfy to power application requirements. Antenna mismatch effect has been evaluated using an active load-pull bench. This filter is connected in series to power amplifier to form a prototype of power amplifier module for GSM/EDGE standard in the DCS frequency band. The power amplifier is realized using STMicroelectronics 0.25 mum BiCMOS technology

Scalable highly flexible WDM switch for ONoC architectures

An Optical Network on Chip (ONoC) relies on a switch that is capable of routing information from one element of the chip to another one, presenting both high data rate and reduced latency during transmission. One efficient way to achieve such functionality, is to combine elementary 4x4 switches to form a general YxY switch. We propose here to enhance this elementary block into a reconfigurable non-blocking 4x4 switch that can take advantage of Wavelength Division Multiplexing to improve its global data rate. For added flexibility, we ensure wavelength granularity so that each connection adapts the number of wavelength taken to its needs. On the one hand, in a single wavelength configuration, we achieve the first fully non-blocking 4x4 switch with double-rings that is compared to state of the art achievements. On the other hand, in a n-wavelengths WDM configuration, we demonstrate the behavior of our reconfigurable nonblocking granular WDM switch with double or single rings. Each ring (or double ring) is thermally tuned during a setup step, to place the resonant peak exactly where expected, to ensure stability of the switch. This architecture is scalable at will, and can be used in a YxY n-wavelengths switch for reconfigurable architectures, that could then benefit from WDM’s increased data rate for applications in High Performance Computing.

0.18-µm CMOS driver optimization for maximum data rate under power and area constraints

This paper presents a Mach-Zehnder-based transmitter in 0.18 µm CMOS. An asymmetric driver is proposed to achieve a large output swing on the optical modulator. The logical effort method was applied on each driver block in order to optimize the propagation delay. The driver characteristics are analyzed based on slew-rate limitation. The speed-power-area trade-off is highlighted and enables to adjust the driver design according to specified constraints. Driver performance obtained with early-design-stage equations is compared to post-layout simulations. Good agreement is demonstrated which validates the proposed sizing methodology.

Optimization of power coupling coefficient of a carrier depletion silicon ring modulator for WDM optical transmissions

The presented method allows to evaluate the impact of power coupling on the performances of a carrier depletion ring resonator transmitter. From a measurement-based modulator model, coupling coefficient is varied and optimized maximizing modulation amplitude and reducing the impact of its process variability.

Impact of process variability of active ring resonators in a 300mm silicon photonic platform

We study the process variability impact of silicon ring modulators on resonance wavelength, which is a key parameter to design WDM communication systems based on those devices.