Pascal Fornara

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching degradation in sub-threshold mode, these parasitic transistors, in case of hump effect, have to be considered.

Influence of various process steps on the reliability of PMOSFETs submitted to negative bias temperature instabilities

Abstract In this paper, we analyze the impact of various process steps on the reliability of PMOSFET’s submitted to Negative Bias Temperature Instabilities stress conditions. We give some evidence of the complete thermal anneal of interface states induced by NBTI and investigate the influence of the oxide thickness and of the final forming gas anneal. Then we show a NBTI lifetime improvement after a fluorine implant through the gate and an arsenic bulk doping value increase.

Dopant Diffusion during Amorphous Silicon Crystallization

We have investigated the redistribution of B during the crystallization of an amorphous Si layer homogeneously doped with P. The redistribution of B only occurs for concentrations lower than 2 × 1020 at cm−3. Crystallization leads to a non “Fickian” redistribution, allowing an abrupt interface between the regions doped and undoped with B. Once the crystallization is ended, B diffuses through the layer in the type B regime with a coefficient which is in agreement with the literature data for diffusion in polycrystalline Si. Although the P distribution is homogeneous in the entire layer, for a temperature as high as 755 °C, P diffuses towards the region the most concentrated in B. The B and P interactions are interpreted as chemical interactions.

Gate Voltage Matching Investigation for Low-Power Analog Applications

On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.

Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area

Low power analog applications are often designed under threshold and can be degraded by hump effect. This effect is explained through device dimensions and body bias studies. A MOSFET matching improvement in sub-threshold area is demonstrated with active “multi-fingers” test structure.

Octagonal MOSFET: Reliable device for low power analog applications

Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; VT matching degradation due to hot carrier stress is also improved with an octagonal design.

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, VT shift due to Hot Carrier Injection stress is accelerated on small width devices. VT matching is also degraded during stress as a function of VT deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.

Mechanical–Electrical Measurements and Relevant Test Structures for Sensing Interconnect Stress Effects in CMOS Technology

For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active regions of silicon. Coupled mechanical–electrical measurements are performed to evaluate the impact of stress at circuit and device levels. This mismatch originated by interconnects metal lines stress is measured through the use of piezoresistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach.

Sensing mobility mismatch due to local interconnect mechanical stress in CMOS technology

For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active region of silicon. This mismatch originated by interconnects metal lines stress is measured through the use of piezo-resistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach.

Stress Development and Relaxation during Reaction of a Cobalt Film with a Silicon Substrate

Thin metal films react with silicon substrates to form various metal silicides. The sequence and kinetics of phase formation are still an area of intense research. Comparatively much less work has been done on the issue of stress development caused by the appearance of these new phases. A detailed review of the subject has been done ten years ago. We present here recent results obtained on Pd-Si, Co-Si, Ni-Si and discuss them in the light of what is known today on the elastic and plastic properties of thin films. A simple model published by S. - L. Zhang and F. M. d’Heurle takes into account the simultaneous stress formation due to the reaction and the relaxation of these stresses. It provides a qualitatively satisfying picture of stress evolution at least for the first phase which forms. The model relies on two basic elements: 1) stress formation due to the formation of a new phase, and 2) the stress relaxation mechanism at work in the growing silicide film. The sign of the stress can be understood from the variation in volume that occurs at the growing interface(s). The stress relaxation mechanisms at work in a growing film are complex. They are highly dependent on the microstructure (as we have shown when comparing Pd/Si(001) and Pd/Si (111)) but should be also highly size dependent (e.g. dislocation glide is more difficult in small scale structures). Inhomogeneous plastic relaxation in polycrystalline silicide films may be an important issue.