Jean Marc Gallière

Boolean and current detection of MOS transistor with gate oxide short

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short

This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects in realistic digital circuits. Based on the electrical analysis of the defect behavior, a comprehensive method for the model construction is detailed. It is shown that the behavior of the proposed model matches in a satisfactory way the behavior of a defective transistor including the random parameters of the defect.

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect

In this paper, we analyze the electrical behavior of logic gates in presence of defect for different technologies. The final objective is to compare the defect detectability in a traditional planar Bulk technology, the emerging FDSOI and FinFET technologies. We implemented similar design in each technology and compared the electrical behavior with the same resistive short defect.

A 2-D VHDL-AMS Model for Disk-Shape Piezoelectric Transducers

Piezoelectric materials are widely used for many applications such as sensors, actuators. Today, their integration in microelectronics processes like CMOS requires the development of advanced realistic behavioral models. Until now, these models were limited to only one ceramics operation mode, i.e., thickness or planar. Moreover, the robustness of piezo-electronic system cannot be adequately addressed as long as models are not improved, in particular by taking into account further real phenomena. This article proposes to merge, in a new behavioral model, the two operation modes. It is demonstrated that the electrical behavior of the proposed model is in very good agreement with the real ceramic behavior.

Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurations

In this paper, we analyse the impact of voltage, temperature and body-biasing on the detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a 28nm UTBB FDSOI (Ultra-Thin Body & BOX Fully-Depleted Silicon-on-Insulator) technology. We implemented a similar design in each configuration and compared their electrical behaviors with the same resistive short defect. In addition, this work focuses on determining the individual as well as the combined improvements brought by voltage, temperature and body-biasing settings for achieving the maximum coverage of the resistive short defects.

Delay testing viability of gate oxide short defects

Gate Oxide Short (GOS) defects are becoming predominant as technology is scaling down. Boolean and IDDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the GOS as a function of the GOS resistance and location. It is demonstrated that i) GOS has a significant impact on gate delay, ii) GOS located close to the source of the transistor and with small resistance has very high impact.

Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies

Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.

Analysis of short defects in FinFET based logic cells

FinFET technology has become the most promising semiconductor technology alternative to CMOS planar at highly scaled nodes (e.g. below 20nm). FinFET technology offers higher performance with lower leakage thanks to a better channel control obtained by wrapping a metal gate around a thin fin. In this paper, bridge defects in FinFET based logic cells are investigated. The impact of the use of Middle-Of-Line (MOL) interconnections and multi-fin and multi-finger devices pose a challenge on the detection of bridge defects. They influence the likelihood of occurrence of these defects, and make them more difficult to detect than in CMOS planar technology. Even more some defects unlikely to appear in planar CMOS now become more likely to occur. A metric called Bridge Defect Criticality (BDC) is used to identify the most critical bridge defects. Actions may be taken over these defects to increase their fault tolerance or testability.

A roaming memory test bench for detecting particle induced SEUs

In this paper, we propose a memory based test bench able to record soft errors that may occur to modern circuits in a certain environment. This system allows a good flexibility from different points of view. It is conceived to be modular, programmable, low power consuming and portable. Consequently, it can operate in various experimental conditions such as under artificial sources of particles as well as in natural ambience, from the earth surface to spatial environment.

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

Since 22nm technology node, FinFET technology is an attractive candidate for high-performance and power-efficient applications. This is achieved due to better channel control in FinFET devices obtained by wrapping a metal gate around a thin fin. In this paper, we investigate the detectability of bridge defects in FinFET based logic cells that make use of Middle-Of-Line (MOL) interconnections and multi-fin and multi-finger design strategies. The use of MOL to build the logic cells impacts the possible bridge defect locations and the likelihood of occurrence of the defect. Some defect locations unlikely to appear in planar CMOS now become more likely to occur due to the use of MOL. It is shown that these defects are difficult to be detected. The detectability of bridge defects has been analyzed for gates with different drive strengths and fan-in, and also extended to the different type of gates. A metric called Bridge Defect Criticality (BDC) is used to identify the most harmful bridge defects. This metric depends on the degree of detectability and likelihood of occurrence of a bridge defect. More design and/or test effort may be dedicated to those defects with higher a value of the BDC metric to improve product quality.