Jean-Philippe Colonna

Thermal performance of 3D ICs: Analysis and alternatives

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

Using TSVs for thermal mitigation in 3D circuits: Wish and truth

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration

Wafer level molding is an important process step in the chip on wafer approach and seems currently required in stacking first process flow. Thermo-mechanical properties of molding material has to be controlled to limit stress induce by CTE mismatch with silicon wafer and also to assure planarization and protection functions. 2D and 3D finite element simulations have been performed to evaluate strain and stress impact at wafer level of material properties of silicone based and epoxy based molding compounds. Impacts of Si interposer thickness, design and chips arrangement on wafer warpage are presented and compared with experimental results.

Thermal correlation between measurements and FEM simulations in 3D ICs

This paper presents a comparison between electrical measurements, which are carried out with embedded in-situ sensors, and thermal numerical simulations. The objectives of this study are firstly to calibrate the Finite Element model by comparing the measurement results with those from simulations through a Design Of Experiments (DOE), and then to provide thermal recommendations on the studied parameters thanks to the calibrated numerical model. The primary objective of the DOE is to quantify the sensitivity of modeling parameters. Results show a strong influence of the silicon thickness, the convective heat transfer coefficient of the bottom surface, the thickness of the thermal insulation and the position of the hot spots relative to the sensors. The boundary conditions, particularly the heat transfer coefficient are also identified as significant parameters. Once the main factor set determined, the second objective of this study is to weight quantitatively the influence of key parameters. Finally, by providing a numerical and experimental comparison, this paper provides validated values of boundary conditions to be applied in the numerical simulations. These are considered to be the most difficult to obtain, while they have a huge influence on the simulation results, and this work allows to provide reliable thermal recommendations on designs to manage self-heating challenges.

Assessment of a heat spreading solution for hot spots cooling in compact packages

Heat generation in integrated circuits has become in few decades one of the most limiting factors for performance improvement in mobile device components, such as cell phones or tablets. In these devices, heat dissipation is limited to a few Watts as state of art cooling systems, such as heat-sinks or fans, do not fit with the dimensional and power consumption constraints. Amongst the solutions proposed for circuit cooling, the implementation of heat spreaders is probably the most suitable alternative for compact packages due to their ease of manufacturing and low cost. The objective of this work is therefore to study the performance of a high thermal conductivity layer directly integrated at the die level in the scope of short term industrial implementation. In particular, we compare both the hotspot temperature reduction and the temperature profile of the die using either copper or a graphite based material. Temperature reductions over 80°C have been measured for the best case scenario, with a thermal resistance enhancement of 61% at the die stack level. Finite volume simulations are finally presented in order to explain the thermal flux of the system.

A comprehensive platform for thermal studies in TSV-based 3D integrated circuits

We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.

Towards alternative technologies for fine pitch interconnects

This study focuses on alternative technologies for fine pitch 3D interconnect. These technologies are: μ-inserts (insertion of a nickel cylinder in Aluminium pad), μ-tubes (insertion of a hard tube in Aluminium pad), Transient Liquid Phase (TLP) bonding (whole solder reacts to form intermetallic compound) and copper direct bonding. In the first part the process flow is described. Then electrical performances are presented, including a comparison of the Kelvin resistance for each technology. The next part presents reliability considerations, where the failure modes and the weaknesses of each interconnect technologies are described. The mechanical impact of insertion technologies is also studied.

Thermo-mechanical assessment of copper and graphite heat spreaders for compact packages

Graphite-based materials have been proved to be an enhancement over copper heat spreaders when directly integrated at the silicon level. However, not only they outdo copper in terms of thermal performance, but their in-plane CTE (coefficient of thermal expansion) is much closer to that of silicon. As a result, mechanical stress due to deformation mismatches is reduced during thermal cycling. Thus, thermal interface thickness can be reduced to optimize the heat flow from the hotspot. Heat management of 3D structures implies several challenges. The silicon die and intertier thickness are limited by the vertical connexions height in these heterogeneous stacks. These constraints will also imply strongly thinned heat spreaders and thermal interfaces in a future intertier implementation. This work investigates the thermo-mechanical constraints of integrating a heat spreader at the die level. Copper and PGS (pyrolytic graphite sheet) heat spreaders are compared. Their deformation subjected to thermal cycling is measured experimentally via Thermo-Moiré measurements. The differences in the deformation between the silicon die, molding and the substrate are also measured.

Graphite-based heat spreaders for hotspot mitigation in 3D ICs

Heat dissipation is frequently pointed as one of the main challenges in the promising 3D integration technology. The very thin dies required to integrate high density TSVs reduce the heat dissipation capacity of the 3D stack and may provoke exacerbated hotpots. This work investigates the use of graphite-based heat spreaders to mitigate the strong hotspot dissipation issues in advanced 3D ICs. Graphite-based materials present high in-plane thermal conductivity and can be integrated into 3D stacks to compensate the poor heat spreading capacity of the thinned silicon dies. Silicon measurements are used to confirm this is a feasible and effective method for thermal management. Numerical simulations for a variety of circuit, application and integration configurations indicate this is an effective approach for hotspot mitigation in 3D ICs. Results for a memory-on-logic 3D circuit indicate a reduction of up to 40% in the peak temperature.