Vincent Fiori

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

Since the 90-nm CMOS technology node, the strained nitride capping layer (i.e., the contact etch stop layer, CESL) is used as a stress-engineering booster that enables transistor improvement. This paper presents a complete mechanical simulation work explaining how the CESL transmits its intrinsic stress to the Si channel. First, it is demonstrated that the CESL stress transmission is the outcome of several CESL parts acting separately (direct effect) or in association (indirect effect) without neglecting the corner effects for small transistors. Then, all the different contributions of these CESL parts on the stress transfer way for long and short channels are explained. Finally, some guidelines are given for a n optimization of the usage of CESL

A multi scale finite element methodology to evaluate wire bond pad architectures

This work focuses on a multi scale finite element method (FEM) in order to model the wire bonding process. The methodology and results aiming at understanding and predicting the bond pad failures are detailed. Due to the very detrimental aspect ratios involve in the wire bonding process modeling, the use of a multilevel technique is mandatory. However, results highlight that precautions are needed at the macro scale when choosing the representative unit cell (RUC) during the homogenization step. More precisely, a simple law of mixture leads to a wrong evaluation of the displacements at the global scale and impacts strongly the local stress field. The FE method is applied in a linear three dimensional analysis. Both thermal and force loadings are tested and their contributions are discussed on several wire bond pad layouts.

3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments

This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in the copper/low-k stack are evaluated. The modeling strategy also includes an in-house developed energy based analysis. For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, several bond pad architectures have been implemented and wire bonded on a test vehicle. It was found a significant effect of the copper/low-k design on peeling failure rates, in particular with severe bonding conditions. In this paper, typical modeling results are presented. Contrary to stress based one, the energy based analysis shows a better ability to forecast the observed failed interface. From simulation results obtained, it is confirmed that the bonding process plays major role in the peeling failure, despite the fact that most of them are observed during the wire pull test. Failure mechanisms are also proposed. Then, the implemented pad structures are evaluated and analyzed. Both general trends and architecture ranking are provided. Simulations are then faced to experimental results and a full agreement is found. The complementary nature of the energy based failure criteria is again highlighted through a clearer discrimination of the tested structures. Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

In this paper, we present a highly-performant PMOS transistor architecture featuring a buried strained SiGe layer (stressor) underneath the Si channel and in between the epitaxially grown Si S/D regions. This stressor together with the shallow trench isolation (STI) induces pseudo-biaxial compressive stress in small devices Si channel. A completely different behaviour compared to bulk-Si devices is shown. Transistors featuring a 50nm gate length, a 1.5nm physical gate oxinitride and an active area width of 0.28/spl mu/m demonstrate drive currents up to 740/spl mu/A//spl mu/m with only 48nA//spl mu/m Ioff at a supply voltage of 1.4V. Those results, regarding the oxide thickness, are in the range of the best ever reported. Moreover, this solution provides easy co-integration possibilities between HP, GP and LP (bulk-like or SON: silicon-on-nothing) devices on the same chip.

Using TSVs for thermal mitigation in 3D circuits: Wish and truth

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

New challenges and opportunities for 3D integrations

From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

This paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness.

Numerical Analysis of the Reliability of Cu/low-k Bond Pad Interconnections Under Wire Pull Test: Application of a 3D Energy Based Failure Criterion

Due to size reduction in die manufacturing and introduction of brittle dielectric materials, crack related failures occur currently, mainly in interconnect levels. By means of Finite Element (FE) simulations, an energy based failure criterion named Nodal Release Energy (NRE) Method, inspired by the so-called Area Release Energy (ARE) one developed by Philips Applied Technologies, is used to numerically predict the mechanical related failures. More precisely, the failure index is applied to investigate wire bonding induced peeling. In this paper, the NRE method is presented and its added value to forecast delamination failures in a typical microelectronics stack is demonstrated. The NRE method is related to fracture mechanics and founded on propagation approach. Two FE calculations are used to evaluate the energy quantity: an uncracked and cracked one. In the latter model, a virtual crack is inserted. Aiming to compare the NRE values with known physical quantities experimentally measured such as critical adhesion energy, a relation bridging the gap from NRE to the Energy Release Rate is given. This relation is based on the crack extension method and relates to Griffith theory. The accuracy of the NRE method is investigated through comparisons with 2D and 3D analytical cases. Results show that the method provides a good approximation. The NRE behaviour with respect to key numerical parameters will be studied. At last, a typical bond pad structure under a wire pull test is simulated. Both stress and energy based analyses are carried out. The critical interface is investigated with both post processing methods. Results based on the energy criterion show that delamination interface is in agreement with experimental observations, in contrast to stress based values. However, it is also shown that simulation results can depend on the prescribed crack length, suggesting a accurate definition of the cracked model. The main assumptions done in this study are discussed, trying to define the associated uncertainties, particularly residual stress and crack morphology features. Finally, the added insights provided by NRE method and its ability to help in design and process development for advanced IC technologies are demonstrated.

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits

This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.

Electromigration induced failure mechanism: Multiphysics model and correlation with experiments

In advanced semiconductor devices, most of the reliability issues in interconnect occurs at a very local scale, especially voiding phenomenon in copper lines induced by electromigration. Hence, a better understanding of mechanism governing electromigration is needed for developing more accurate lifetime models. In this paper, finite element simulations are carried out in that frame. Firstly, a model of vacancy migration is proposed. Thermal, stress and concentration gradients, and electrical current driven forces are considered. A realistic configuration of electromigration in a small segment of copper line is studied. The local vacancy accumulation at the cathode is observed. Distinct diffusion paths (lattice, grain boundary and interface) are implemented in a (111) oriented copper grains; it provide more realistic vacancy kinetics and it highlight large heterogeneity of concentration, which is responsible for void nucleation. Secondly, a model of void evolution, coupled with the transport vacancy model is implemented. To distinguish both metal and void phases, an order parameter field is introduced. The motion of the diffuse interface metal/void is solved by mean of the so-called level set method. The normal velocity of the front is directly computed thanks to the local vacancy concentration. Finally, the evolution of the line resistance in function of time and the void shape is output and analyzed. By facing simulation results with measurements and observations, a good agreement is revealed and efficiency of the implemented model is demonstrated.