Venkatesh Srinivasan

A 531 nW/MHz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

We present a 128/spl times/32 four-quadrant programmable current-mode analog vector-matrix multiplier (VMM). The proposed multiplier cell operates on a 3.3 V supply, consumes 531 nW/MHz and is linear over two decades of current range. Programmability and non-volatile weight storage is obtained by using floating-gate transistors. Experimental results for a full image discrete cosine transform (DCT) using the proposed architecture is presented. The IC prototype was fabricated in a 0.5 /spl mu/m CMOS process and occupies 0.83 mm/sup 2/ of area.

A precision CMOS amplifier using floating-gates for offset cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifiers architecture. The offset voltage of a single-stage folded cascode amplifier is reduced to plusmn25 muW in a 0.5mum digital CMOS process. The offset voltage drift is 0.5 muV over a period of 10 years at 25degC and varies by a maximum of 130muV over a temperature range of 170degC

A Floating-Gate-Based Programmable CMOS Reference

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-mum CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of plusmn40 muV . Experimental results indicate a temperature sensitivity of approximately 53 muV/degC for a nominal reference voltage of 0.4 V over a temperature range of -60degC-140degC.

Floating-gates transistors for precision analog circuit design: an overview

This paper presents an overview of floating-gate transistors with an emphasis on using them as programmable elements to correct mismatch inherent in analog circuit design. The design methodology is such that floating-gate MOSFETs play the role of programmable elements while forming an inherent part of the circuitry of interest, as well. Such an approach results in a compact architecture with minimal additional power. Accurate programming that is key to a successful implementation is discussed along with experimental results demonstrating floating-gate charge retention. An overview of several circuit design examples is provided to demonstrate the feasibility of using floating-gate transistors for precision analog circuit design

Linear current-to-voltage and voltage-to-current converters

Current-voltage (I-V) and voltage-current (V-I) converters for use in current-mode analog integrated circuits are described. The proposed I-V converter has 2.4 decades of linear range, a THD of 0.82% and a bandwidth of 10 MHz. The V-I converter exhibits 5 decades of linear range with a 30 MHz bandwidth at a 1muA bias current and introduces no additional non-linearities. Both circuits have been implemented in a 0.5mum standard digital CMOS process

Low-power realization of FIR filters using current-mode analog design techniques

This work demonstrates the feasibility of low-power analog FIR filters using current-mode techniques. Preliminary results from the proposed filter indicate a power consumption that is much lower than alternate digital implementations at 20MSPS making it attractive for portable applications. The FIR filter comprises of a current-mode sample-and-hold configured as a delay element followed by an analog multiplier. Results from an 8-tap linear phase filter and a 16-tap non-linear phase filter are shown to match well with the ideal filter responses.

A Compact Programmable CMOS Reference With ±40μV Accuracy

A compact programmable CMOS voltage reference that is determined by the charge difference between two floating-gate transistors is introduced in this paper. A prototype circuit has been implemented in a 0.35μm CMOS process; reference voltages ranging from 50mV - 0.6V have been achieved and initial accuracy of ±40muV has been demonstrated as well. Experimental results indicate a temperature sensitivity of approximately 53μV/degC for a nominal reference voltage of 0.4V over a temperature range of -60°C to 140°C

An adaptive analog synapse circuit that implements the least-mean-square learning rule

In this paper a compact adaptive analog synapse circuit that implements the least-mean-square (LMS) learning rule is described. Basic simulation results demonstrate the LMS learning rule in the proposed circuit. An adaptive linear combiner that uses the proposed synapse is shown to learn a square wave that matches closely with the desired target. Issues of weight decay and its implications to the design of the synapse circuit are presented as well. The synapse is designed in a 0.5 /spl mu/m CMOS technology.

Minimizing Phase Noise Variation in CMOS Ring Oscillators

The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 μm CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillators output frequency range.

A novel programmable frequency divider based on analog counter

An analog programmable frequency divider (APFD) that is based on the concept of an analog counter is described. The divide ratio is set using the analog counter and a toggle flip-flop. A prototype programmable divider has been implemented in a 0.5mum standard digital CMOS process with divide ratios ranging from 16-30 in steps of 2 for a maximum input frequency of 10MHz. The divide ratio exhibits a weak logarithmic dependence on process, voltage and temperature (PVT) variations that can be addressed using resistor trimming. Simulation results have been provided that demonstrate both the functionality and feasibility of the proposed divider