Nelson Fan

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

Stencil printing of underfill for flip chips on organic-panel and Si-wafer assemblies

A high-throughput method of post-assembly underfill is presented in this study. Emphasis is placed on the proposal of a specially designed stencil to print the underfill material for flip chips on large organic-panel and Si-wafer assemblies. After printing, the organic-panel or Si-wafer assemblies are placed on a hot plate for the underfill to totally fill the space between the chips, solder joints and substrates by capillary action, and then cured. The printing time is in a matter of seconds and hundreds or even thousands (depending of chip size and panel- and wafer-substrate size) of assemblies are printed. The cured assemblies are characterized by the C-SAM (C-Mode scanning acoustic microscopy), x-ray, shear test, cross-sectioning, and SEM (scanning electron microscopy). The effects of the viscosity, thermal enhancement, and multiple prints of underfills are examined. It is found that stencil printing of underfill for flip chips on organic-panel and Si-wafer substrates is a very high-throughput, simple, and low cost process.

Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates

A high-throughput method of post assembly underfill is presented in this paper. Emphasis is placed on the proposal of a specially designed stencil to print the underfill material for flip chips on large organic-panel and Si-wafer assemblies. After printing, the organic-panel or Si-wafer assemblies are placed on a hot plate for the underfill to totally fill the space between the chips, solder joints, and substrates by capillary action, and then cured. The cured assemblies are characterized by the C-mode scanning acoustic microscopy, X-ray, shear test, cross sectioning, and scanning electron microscopy. The effects of the viscosity, thermal enhancement, and multiple prints of underfills are examined. It is found that stencil printing of underfill for flip chips on organic-panel and Si-wafer substrates is a very high-throughput, simple, and low-cost process.