Jeffrey Douglas Brown

IBM Power Edge of Network Processor: A Wire-Speed System on a Chip

The IBM Power Edge of Network processor combines the attributes of a general-purpose processing subsystem with function accelerators and networking interfaces to create a system on a chip thats targeted for applications at the edge of network. This article discusses in detail the processing, accelerator, and network interface subsystems and explores applications well suited to the PowerEN processor.

Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.

High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology

The ability to meet the demand for improved microprocessor performance is made difficult due to the simultaneous need not to increase power consumption. In order to meet these conflicting demands, IBM introduced a 90 nm dual stress liner CMOS technology to improve performance without increasing power consumption (Santiago et al., 2006). In IBMs 300 mm fab, this technology was introduced on multiple microprocessors, designed by different design groups with different architectures. These microprocessors, which were originally designed for a single liner technology, were optimized for systematic yield, power/performance; circuit limited yield (CLY), and random defect limited yield. The benefit of the dual stress liner technology is demonstrated in the power/performance characteristic of a dual core microprocessor and the successful technology ramp is demonstrated by yields of two microprocessors

High Performance Processor Development for Consumer Electronics Game Processor Perspective

The development of customized solutions for optimized consumer electronics applications like game processors is pushing the boundaries of VLSI in many ways. The author will describe architectural, circuit, packaging and manufacturing challenges focusing on why game processors are different and require unique solutions. A historical perspective of gaming and entertainment systems and their intersection with leading edge processor design will provide insight into future trends and needs in VLSI design.

The IBM power edge of Network™ processor: A wire-speed system-on-a-chip with 16 Power™ cores / 64 threads and optimized HW acceleration

Presents a collection of slides covering the following topics: Network processor; IBM power edge; wire-speed system-on-a-chip; interconnect architecture; PowerPC processing element architecture; DDR3 DRAM controller; accelerator architecture; accelerator interface; compression/decompression; crypto data mover; XML engines; packet processor architecture; and PCI-Express.

GC hard mask open tool CD monitoring and matching

Critical dimension control of gate stack hard mask open is essential to good process yield. A sector monitoring scheme was developed to provide prompt feedback of any litho or etch process drift to protect product jobs. To match GC hard mask open CDs from multiple etch tools oxygen gas flow was employed to calibrate the CDs and provide the matching conditions for all the etch chambers.