Jeffrey H. Sloan

CDM failure modes in a 130nm ASIC technology

CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.

ESD design automation for a 90nm ASIC design system

Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.

Design automation to suppress cable discharge event (CDE) induced latchup in 90nm CMOS ASICs

Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.