Jeffrey T. Wetzel

Kinetics of copper drift in low-/spl kappa/ polymer interlevel dielectrics

This paper addresses the drift of copper ions (Cu/sup +/) in various low-permittivity (low-/spl kappa/) polymer dielectrics to identify copper barrier requirements for reliable interconnect integration in future ULSI. Stressing at temperatures of 150-275/spl deg/C and electric fields up to 1.5 MV/cm was conducted on copper-insulator-silicon capacitors to investigate the penetration of Cu/sup +/ into the polymers. The drift properties of Cu/sup +/ in six industrially relevant low-/spl kappa/ organic polymer insulators-parylene-F, benzocyclobutene, fluorinated polyimide, an aromatic hydrocarbon, and two varieties of poly(arylene ether)-were evaluated and compared by capacitance-voltage, current-time, current-voltage, and dielectric time-to-failure measurements. Our study shows that Cu/sup +/ drifts readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. Among these polymers, the copper drift barrier property appears to be improved by increased polymer crosslinking and degraded by polar functional groups in the polymers. A thin nitride cap layer can stop the drift. A physical model has been developed to explain the kinetics of Cu/sup +/ drift.

Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).

Copper drift in low-K polymer dielectrics for ULSI metallization

This paper reports the drift of Cu ions in various low-permittivity polymer dielectrics to identify Cu barrier requirements for future ULSI integration. Bias-temperature stressing was conducted on Cu-insulator-semiconductor capacitors to investigate Cu+ penetration into the polymers. Our study shows that Cu/sup +/ ions drift readily into poly(arylene ether) and fluorinated polyimide, but much more slowly into benzocyclobutene. A thin nitride cap layer can stop the drift. A physical model has been developed to explain the kinetics of Cu/sup +/ drift.

Electrical leakage at low-K polyimide/TEOS interface

The effect of low-K polymer passivation on electrical leakage was investigated to evaluate the reliability of polymer integration on device wafers. Polyimide passivation over Al(0.5% Cu) interconnects inlaid in TEOS increases the intralevel leakage current mainly along the polyimide/TEOS interface. Moisture absorbed in the polyimide further increases the inter facial as well as bulk leakages. These findings emphasize the importance of separating interconnects from direct contact with polyimide/TEOS interfaces to alleviate electrical isolation problems in multilevel interconnect architecture that employs low-K polymer dielectrics.

EVALUATION OF COPPER PENETRATION IN LOW- κ POLYMER DIELECTRICS BY BIAS-TEMPERATURE STRESS

The industry is strongly interested in integrating low- κ dielectrics with Damascene copper. Otherwise, with conventional materials, interconnects cannot continue to scale without limiting circuit performance. Integration of copper wiring with silicon dioxide (oxide) requires barrier encapsulation since copper drifts readily in oxide. An important aspect of integrating copper wiring with low- κ dielectrics is the drift behavior of copper ions in these dielectrics, which will directly impact the barrier requirements and hence integration complexity. This work evaluates and compares the copper drift properties in six low- κ organic polymer dielectrics: parylene-F; benzocyclobutene; fluorinated polyimide; an aromatic hydrocarbon; and two varieties of poly(arylene ether). Copper/oxide/polymer/oxide/silicon capacitors are subjected to bias-temperature stress to accelerate penetration of copper from the gate electrode into the polymer. The oxide-sandwiched dielectric stack is used to overcome interface instabilities occurring when a low- κ dielectric is in direct contact with either the gate metal or silicon substrate. The copper drift rates in the various polymers are estimated by electrical techniques, including capacitance-voltage, current-voltage, and current-time measurements. Results correlate well with timeto-breakdown obtained by stressing the capacitor dielectrics. Our study shows that copper ions drift readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. A qualitative comparison of the chemical structures of the polymers suggests that copper drift in these polymers may possibly be retarded by increased crosslinking and enhanced by polarity in the polymer.

Electrical Reliability of Cu and Low- K Dielectric Integration

The recent demonstrations of manufacturable multilevel Cu metallization have heightened interest to integrate Cu and low- K dielectrics for future integrated circuits. For reliable integration of both materials, Cu may need to be encapsulated by barrier materials since Cu ions (Cu + ) might drift through low- K dielectrics to degrade interconnect and device integrity. This paper addresses the use of electrical testing techniques to evaluate the Cu + drift behavior of low- K polymer dielectrics. Specifically, bias-temperature stress and capacitance-voltage measurements are employed as their high sensitivities are well-suited for examining charge instabilities in dielectrics. Charge instabilities other than Cu + drift also exist. For example, when low- K polymers come into direct contact with either a metal or Si, interface-related instabilities attributed to electron/hole injection are observed. To overcome these issues, a planar Cu/oxide/polymer/oxide/Si capacitor test structure is developed for Cu + drift evaluation. Our study shows that Cu + ions drift readily into poly(arylene ether) and fluorinated polyimide, but much more slowly into benzocyclobutene. A thin nitride cap layer can prevent the penetration.

Interfacial Adhesion Study of Porous Low-K Dielectrics to CVD Barrier Layers

The present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 2 ) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

Integration Challenges of Inorganic Low-K (K≤2.5) Materials with Cu for Sub-0.25µm Multilevel Interconnects

The recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.