Changsup Ryu

Kinetics of copper drift in low-/spl kappa/ polymer interlevel dielectrics

This paper addresses the drift of copper ions (Cu/sup +/) in various low-permittivity (low-/spl kappa/) polymer dielectrics to identify copper barrier requirements for reliable interconnect integration in future ULSI. Stressing at temperatures of 150-275/spl deg/C and electric fields up to 1.5 MV/cm was conducted on copper-insulator-silicon capacitors to investigate the penetration of Cu/sup +/ into the polymers. The drift properties of Cu/sup +/ in six industrially relevant low-/spl kappa/ organic polymer insulators-parylene-F, benzocyclobutene, fluorinated polyimide, an aromatic hydrocarbon, and two varieties of poly(arylene ether)-were evaluated and compared by capacitance-voltage, current-time, current-voltage, and dielectric time-to-failure measurements. Our study shows that Cu/sup +/ drifts readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. Among these polymers, the copper drift barrier property appears to be improved by increased polymer crosslinking and degraded by polar functional groups in the polymers. A thin nitride cap layer can stop the drift. A physical model has been developed to explain the kinetics of Cu/sup +/ drift.

Kinetics of copper drift in PECVD dielectrics

We quantified the drift of Cu ions into various PECVD dielectrics by measuring shifts in capacitance-voltage behavior after subjecting Cu-gate MOS capacitors to bias-temperature stress. At a field of 1.0 MV/cm and temperature of 100/spl deg/C, Cu ions drift readily into PECVD oxide with a projected accumulation of 2.7/spl times/10/sup 13/ ions/cm/sup 2/ after 10 years. However, in PECVD oxynitride, the projected accumulation under the same conditions is only 2.3/spl times/10/sup 10/ ions/cm/sup 2/. These findings demonstrate the necessity of integrating drift barriers, such as PECVD oxynitride layers, in Cu interconnection systems to ensure threshold stability of parasitic field n-MOS devices.

Evidence of heteroepitaxial growth of copper on beta-tantalum

Crystallographic orientations between thin-sputtered Cu film and β-Ta adhesion layer have been studied using high resolution electron microscopy and electron diffraction. Tetragonal β-Ta deposited on SiO2 has a strong texture with its closest packed plane (002) parallel to the film surface. On (002) β-Ta, the growth of (111) Cu is preferred. Even though more than 100 β-Ta grains are found under a single Cu grain, the Ta grains under a Cu grain have long range in-plane texture with [330] direction aligned parallel to the [220] direction of Cu. This orientational coincidence is explained by the heteroepitaxial relationship between the hexagonal close-packed atomic array in Cu (111) plane and the pseudohexagonal configuration of β-Ta atoms in (002) plane with a misfit strain of 7.6%.

Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon

This paper presents an ultra-low resistance, high wiring density, through-wafer via (TWV) technology that is compatible with standard silicon wafer processing. Vias as small as 30 µm by 30 µm are fabricated through a 525 µm thick wafer. This results in an aspect ratio for the via that is greater than 17:1. Furthermore, the dc resistance of a single via is less than 50 mΩ. Key fabrication steps, including the silicon dry etch, copper metallization, and photoresist electroplating, are described in detail. As a demonstration of the potential applications of the TWV technology, a novel three dimensional inductor is designed and fabricated. For a 0.9-nH inductor, a quality factor of 18.5 is measured at 800 MHz.

Barriers For Copper Interconnections

The integration of Cu interconnections will require sophisticated structures to prevent Cu from coming into contact with devices. The barriers for Cu also must have good adhesion with dielectric and Cu, and yield desirable microstructure of Cu. This paper discusses several critical barrier requirements and compares the properties of Ta and Ti/TiN barrier systems.

Effect of texture on the electromigration of CVD copper

Changsup Ryu, Alvin L. S. Loke, Takeshi Nogami* and S. Simon Wong Center for Integrated Systems 040, Stanford University, California 94305 415-725-3727: fax: 41 5-725-3383; email: changsup@leland.stanford.edu * On leave from LSI Research Center, Kawasaki Steel Corporation, Japan We have studied the effect of texture on the electromigration lifetime of CVD Cu. Using the proper seed layers, either (1 11) or (200) textured CVD Cu films with similar grain size distributions have been obtained. The electromigration lifetime of (1 11) CVD Cu is about four times longer than that of (200) CVD Cu. The activation energy of electromigration is about 0.8 eV for both (1 11) and (200) CVD Cu films.

Electromigration of submicron Damascene copper interconnects

Summary form only given. This paper compares the microstructure and reliability of submicron Damascene CVD and electroplated Cu interconnects. For CVD Cu, the electromigration lifetime degrades in the deep submicron range due to fine grains constrained by the deposition process. However, electroplated Cu has relatively large grains in trenches, resulting in no degradation of reliability in the deep submicron range. The electromigration performance of electroplated Cu is superior to that of CVD Cu especially for deep submicron Damascene interconnects.

Copper drift in low-K polymer dielectrics for ULSI metallization

This paper reports the drift of Cu ions in various low-permittivity polymer dielectrics to identify Cu barrier requirements for future ULSI integration. Bias-temperature stressing was conducted on Cu-insulator-semiconductor capacitors to investigate Cu+ penetration into the polymers. Our study shows that Cu/sup +/ ions drift readily into poly(arylene ether) and fluorinated polyimide, but much more slowly into benzocyclobutene. A thin nitride cap layer can stop the drift. A physical model has been developed to explain the kinetics of Cu/sup +/ drift.

Barrier/seed layer requirements for copper interconnects

The microstructure of electroplated Cu is highly dependent on the characteristics of underlying barrier and seed layers. A smooth and strongly textured Cu seed layer is needed to promote the development of highly textured, large grains in the electroplated Cu film, even in damascene structures. This microstructure is desired for extended reliability.

Microstructure And Mechanical Properties Of Electroplated Cu Films For Damascene Ulsi Metallization

Copper has been deposited for filling sub-0.5 μm trenches by using electroplating. Electroplating with pulse plating conditions provides the high deposition rate (0.5–1 μm/min) and defect-free filling the 0.25 μm trenches and vias of high aspect ratio (>4:1). Enhanced copper electroplating at the trench bottom has been achieved. The median grain size of electroplated copper was measured to be about 1 jim and the lognormal standard deviation is about 0.4 μm. Strong texture was observed in electroplated Cu film. Low stress of electroplated Cu films and excellent adhesion of plated Cu to sputtered Cu seed were observed.