Jehyuk Rhee

Wide dynamic range and high SNR self-reset CMOS image sensor using a Schmitt trigger

A simple and robust self-reset image sensor design using Schmitt trigger circuit is presented. Offset and reset delay accumulations are compensated effectively so that a self-reset CMOS image sensor can exploit signal-to-noise ratio (SNR) improvement along with its wide dynamic range under multiple resets. It has been designed and simulated using 0.18 mum CMOS technology to show SNR improvement of 22.8 dB with 1000 self-resets. It also provides low power consumption and fewer components for pixel-level image sensor design.

CMOS image sensor array for surface plasmon resonance spectroscopy

A novel surface plasmon resonance (SPR) sensor system using CMOS image sensor array is proposed in this paper. Recently, a simple SPR system was proposed by the author, which achieved high resolution and fast response time using a bi-cell photo-detector. However it requires mechanical adjustment process to balance two signals of the bi-cell before measurement. It requires not only additional time but also additional mechanical control unit, which is a source of the noise. It also suffers from the small linear range. The proposed method chooses a pixel as the center from many pixels, which gives the most balance of bi-cell signal. Therefore no mechanical adjustment is required. The method also overcomes the small linear range problem by switching the center adaptively during the test. Furthermore, it has several advantages of CMOS image sensor such as low cost, low power, and on-chip functionality, which makes the proposed SPR sensor system be a good candidate for field applications. A prototype CMOS image sensor chip with 12bits analog to digital converter is designed and fabricated with 0.5um AMI CMOS technology.

Analysis and Design of a Robust Floating Point CMOS Image Sensor

A robust floating point CMOS image sensor (CIS) is designed and tested. A detailed analysis for signal-to-noise ratio (SNR) of the floating point CIS including the effect of the exponent detection error is presented. Based on the analysis, a simple way to effectively remove the optimum integration time detection error is proposed. In addition, the proposed imager obtains the exponent at the beginning of the image capturing cycle, which provides a logarithmic image of the scene. A 32 times 24 prototype sensor including 4 transistors pixel array, 4 bit static random access memory (SRAM) array, 8 bit ADC and CDS block, and integration time control block was designed and fabricated using standard 0.5 mum CMOS process. It achieved 50.5 dB of dynamic range (DR) enhancement with 32 dB of peak SNR at 30 frames/s.

A new wide dynamic range fixed point ADC for FPAs

CMOS image sensor system has several clear advantages over CCD image sensor system: selective readout, low power, small size, high frame rate, on-chip functionality, and low cost. However CCD image system still dominates over digital camera market, because the CMOS image system has a poor dynamic range (DR) and peak signal-to-noise ratio (SNR). In this paper, we propose a new enhanced DR and peak SNR CMOS image sensor with pixel level analog-to-digital converter (ADC). The proposed reset technique increases the well capacity of the imager. Consequently, DR and peak SNR are increased simultaneously while other DR enhancement schemes increase only DR. We designed and simulated the proposed circuit and achieved 12bit resolution with 1000frames/sec. Power consumption per each pixel is 50nW. DR is enhanced by 36dB and peak SNR is enhanced by 18dB.

A new low switching noise CMOS logic circuits for single-chip CMOS imaging system

In this paper, we present a new low switching noise CMOS logic for on-chip CMOS image sensors, which reduce the switching noise through the substrate. The instantaneous peak current in digital system is the main source of the substrate noise and the injected current noise propagates through highly doped substrate and contaminates the sensitive image sensing systems. AMI 0.5 /spl mu/m CMOS technology is used for the analysis of switching noise. Simulation results show that the proposed logic generates lower ground bounce compare to the other low noise logic circuits. As a result it enables system-on-chip CMOS imaging system to be less susceptible to switching noise than when using other low noise logics.