Jelena Trajkovic

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology

State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

Chameleon: Channel efficient Optical Network-on-Chip

The next generation of MPSoC points to the integration of thousands of IP cores, requiring high performance interconnect for high throughput communications. Optical on-chip interconnect enables significantly increased bandwidth and decreased latency in MPSoC. However, the interface between electrical and photonic devices implies strong layout constraints that may impact the system performance and scalability. In this paper, we propose a novel optical interconnect named Chameleon. The interface simplifies the layout and allows the bandwidth between IP cores to be adapted according to the communication requirements. Compared to related networks, Chameleon demonstrates improved scalability and flexibility at the cost of minor increase in power consumption.

Multi-Optical Network-on-Chip for Large Scale MPSoC

Optical network-on-chip (ONoC) architectures are emerging as promising contenders to solve bandwidth and latency issues in multiprocessor systems-on-chip (MPSoC). However, current on-chip integration technologies for optical interconnect allow interconnecting only dozens of IPs. Scaling with MPSoCs composed of hundreds of IPs thus, relies on unpredictable technological innovations. In this letter, we propose a method that combines multiple ONoCs. Each ONoC is small enough to rely on already existing and proven technologies. We evaluate the approach for various interconnect scenarios, showing that it scales well with the size of the MPSoC architectures.

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)

Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this paper, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers.

Optical crossbars on chip, a comparative study based on worst-case losses

The many‐core design research community has shown high interest in optical crossbar on chip for more than a decade. Key properties of optical crossbars, namely (1) contention‐free data routing, (2) low latency communication, and (3) potential for high bandwidth through the use of wavelength division multiplexing, motivate several implementations of this type of interconnect. These implementations demonstrate very different scalability and power efficiency abilities depending on three key design factors: (1) network topology, (2) considered layout, and (3) insertion losses induced by the fabrication process. In this paper, the worst‐case optical losses of crossbar implementations are compared according to the factors mentioned earlier. The comparison results have the potential to help many‐core system designer to select the most appropriate crossbar implementation according to, for instance, the number of IP cores and the die size. Copyright

Chip-Scale Silicon Photonic Interconnects: A Formal Study on Fabrication Non-Uniformity

Silicon photonic interconnect (SPI) is an attractive alternative for the power-hungry and low-bandwidth metallic interconnect in multiprocessor systems-on-chip (MPSoCs). When employing SPIs for wavelength-division multiplexing (WDM)-based applications, it is essential to precisely align the central wavelengths of different photonic devices (e.g., photonic switches) to achieve a reliable communication. However, SPIs are sensitive to fabrication nonuniformity (a.k.a. fabrication process variation), which results in wavelength mismatches between devices, and hence performance degradation in SPIs. This work presents a computationally efficient and accurate bottom-up approach to study the impact of fabrication process variations on passive silicon photonic devices and interconnects. We first model the impact of process variations at the component level (i.e., strip waveguides), then at the device level (i.e., add-drop filters and photonic switches), and finally at the system level (i.e., passive WDM-based SPIs). Numerical simulations are performed not only to evaluate the accuracy of our method, but also to demonstrate its high-computational efficiency. Furthermore, our study includes the design, fabrication, and analysis of several identical microresonators to demonstrate process variations in silicon photonics fabrication. The efficiency of our proposed method enables its application to large-scale passive SPIs in MPSoCs, where employing time-consuming numerical simulations is not feasible.

Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects

Silicon photonic interconnect (SPI) is a promising candidate for the communication infrastructure in multiprocessor systems-on-chip (MPSoCs). When employing SPIs with wavelength-division multiplexing (WDM), it is required to precisely match different devices, such as photonic switches, filters, etc, in terms of their central wavelengths. Nevertheless, SPIs are vulnerable to fabrication non-uniformity (a.k.a. process variations), which influences the reliability and performance of such systems. Understanding process variations helps develop system design strategies to compensate for the variations, as well as estimate the implementation cost for such compensations. For the first time, this paper presents a computationally efficient and accurate bottom-up method to systematically study different process variations in passive SPIs. Analytical models to study the impact of silicon thickness and waveguide width variations on strip waveguides and microresonator (MR)-based add-drop filters are developed. Numerical simulations are used to evaluate our proposed method. Furthermore, we designed, fabricated, and tested several identical MRs to demonstrate process variations. The proposed method is applied to a case study of a passive WDM-based photonic switch, which is the building block in passive SPIs, to evaluate its optical signal-to-noise ratio (OSNR) under different variations. The efficiency of our proposed method enables its application to large-scale SPIs in MPSoCs, where employing numerical simulations is not feasible.

Quota setting router architecture for quality of service in GALS NoC

Network on Chip (NoC) is a new communication paradigm for emerging multi- and many-core architectures. Despite major benefits, like scalability and power efficiency, it suffers from lack of guaranteed bounded latency. Many contemporary applications, like multimedia and real-time applications, require such a guarantee. The growth of these applications in embedded systems emphasizes the need for guaranteed services in NoCs. Additionally, increasing numbers of cores in NoCs highlights the clock distribution issue. Globally asynchronous locally synchronous (GALS) NoC architectures propose to solve this issue through using asynchronous routers to connect synchronous blocks. This paper presents a novel approach for guaranteed service in a GALS NoC by using router with set port quota. We propose a novel router architecture which facilitates guaranteed latency for accessing shared media. Our simulations show up to 39% improvement in latency, with a negligible (up to 5%) power overhead.

Photonic integrated circuits: A study on process variations

Developing an efficient method and applying it to study several identical microresonators fabricated by electron beam lithography, we quantify the worst-case within-die silicon thickness and resonance wavelength variations to be 1.55 and 2.11 nm, respectively.

Automated generation of custom processor core from C code

We present a method for construction of application-specific processor cores from a given C code. Our approach consists of three phases. We start by quantifying the properties of the C code in terms of operation types, available parallelism, and other metrics. We then create an initial data path to exploit the available parallelism. We then apply designer-guided constraints to an interactive data path refinement algorithm that attempts to reduce the number of the most expensive components while meeting the constraints. Our experimental results show that our technique scales very well with the size of the C code. We demonstrate the efficiency of our technique on wide range of applications, from standard academic benchmarks to industrial size examples like the MP3 decoder. Each processor core was constructed and refined in under a minute, allowing the designer to explore several different configurations in much less time than needed for manual design. We compared our selection algorithm to the manual selection in terms of cost/performance and showed that our optimization technique achieves better cost/performance trade-off. We also synthesized our designs with programmable controller and, on average, the refined core have only 23% latency overhead, twice as many block RAMs and 36% fewer slices compared to the respective manual designs.