Sébastien Le Beux

A Model-Driven Design Framework for Massively Parallel Embedded Systems

Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functionalities. The design of these systems mainly relies on the following challenging issues: first, how to deal with the parallelism in order to increase the performance; second, how to abstract their implementation details in order to manage their complexity; third, how to refine these abstract representations in order to produce efficient implementations. This article presents the Gaspard design framework for massively parallel embedded systems as a solution to the preceding issues. Gaspard uses the repetitive Model of Computation (MoC), which offers a powerful expression of the regular parallelism available in both system functionality and architecture. Embedded systems are designed at a high abstraction level with the MARTE (Modeling and Analysis of Real-time and Embedded systems) standard profile, in which our repetitive MoC is described by the so-called Repetitive Structure Modeling (RSM) package. Based on the Model-Driven Engineering (MDE) paradigm, MARTE models are refined towards lower abstraction levels, which make possible the design space exploration. By combining all these capabilities, Gaspard allows the designers to automatically generate code for formal verification, simulation and hardware synthesis from high-level specifications of high-performance embedded systems. Its effectiveness is demonstrated with the design of an embedded system for a multimedia application.

Multi-Optical Network-on-Chip for Large Scale MPSoC

Optical network-on-chip (ONoC) architectures are emerging as promising contenders to solve bandwidth and latency issues in multiprocessor systems-on-chip (MPSoC). However, current on-chip integration technologies for optical interconnect allow interconnecting only dozens of IPs. Scaling with MPSoCs composed of hundreds of IPs thus, relies on unpredictable technological innovations. In this letter, we propose a method that combines multiple ONoCs. Each ONoC is small enough to rely on already existing and proven technologies. We evaluate the approach for various interconnect scenarios, showing that it scales well with the size of the MPSoC architectures.

Combining mapping and partitioning exploration for NoC-based embedded systems

Networks on Chip (NoC) have emerged as the key paradigm for designing a scalable communication infrastructure for future Systems on Chip (SoC). An important issue in NoC design is how to map an application on this architecture and how to determine the hardware/software partition that satisfies the performance, cost and flexibility requirements. In this paper, we propose an approach that concurrently optimizes the mapping and the partitioning of streaming applications. The proposed approach exploits multiobjective evolutionary algorithms that are fed by execution performances scores corresponding to the evaluated mappings and partitioning ability to pipeline execution of the streaming application. As result, most promising solutions are highlighted for mapping multimedia applications onto a SoC architecture interconnecting 16 nodes through 2D-Mesh and Ring NoC.

Optimizing Configuration and Application Mapping for MPSoC Architectures

Networks on Chip (NoCs) have emerged as the key paradigm for designing a scalable communication infrastructure for future Multi-Processors Systems on Chip(MPSoCs). An important issue in NoC design is how to configure a NoC-based architecture and how to map an application on this architecture in order to satisfy the performance and cost requirements. In this paper, we propose an approach that concurrently optimizes the configuration of NoC-based architectures and the mapping of streaming applications. The proposed approach exploits multiobjective evolutionary algorithms that are fed by execution performances scores corresponding to the evaluated MPSoC configurations and mappings ability to pipeline execution of the streaming application. As an optimization result, most promising configurations and mappings are highlighted. We show results for mapping an image processing application onto a configurable MPSoC architecture. These results highlight MPSoC architectures configured to interconnect up to 12 processors using Crossbar, Mesh and Ring topologies.

Massively parallel processing on a chip

MppSoC is a SIMD architecture composed of a grid of processors andmemories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution of the famous massively parallel systems proposed at the end of the eighties. We claim that today such a machine may be integrated in a single chip. On one side, new design methodologies such as IP reuse and, on the other side, thepossible high level of integration on a chip let us envisage sucha revival. Some improvements of the system architecture are possible because of the high degree of integration: The mppSoC processing elements sharemost of their design with the control processor, the integrated network allows to exchange data between PEs, but also between thecontrol processor and the PE memories, and even to connect the external devices to the system. This paper presents the mppSoC architecture, a cycle-accurate bit-accurate SystemC simulator of this architecture, and a prototype of implementation on FPGA. A complete tool chain and the execution ofsome applications on the simulator and the FPGA implementation validate the modeling choices and show the effectiveness of this design.

System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures

Design trends for next-generation multi-processor systems on chip (MPSoC) point to the integration of a large number of processing elements onto a single chip, requiring high-performance interconnect structures for high-throughput communication. On-chip optical interconnect and 3D die stacking are currently considered to be the two most promising paradigms in this design context. New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design. We investigate design tradeoffs for 3D MPSoC integrating optical networks-on-chip (ONoC) and highlight current and short-term design trends. We also propose a system-level design space exploration flow that takes routing capabilities of optical interconnect into account. The resulting application-to-architecture mappings demonstrate the benefits of the presented 3D MPSoC architectures and the efficiency of our system-level exploration flow.

A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC

Optical on-chip interconnects and 3D die stacking are currently considered to be two promising paradigms for the design of next generation Multi-Processors System on Chip architectures (MPSoC). New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design and prototype. The paper investigates a system-level flow for evaluating design feasibility, interconnect architecture performance and application execution efficiency as early as possible in the MPSoC design cycle.