Jen-Chieh Yeh

A built-in self-repair design for RAMs with 2-D redundancy

This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves as the reconfiguration unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the BISR scheme. The BISR circuit has a low area overhead-about 4.6% for an 8 K /spl times/ 64 SRAM.

A built-in self-repair scheme for semiconductor memories with 2-d redundancy

Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes: the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. The BIRA module also serves as the reconfiguration (address remapping) unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the proposed RA algorithm and BISR scheme. The BISR circuit has a low area overhead—about 4.6% for an 8K 64 SRAM.

Flash memory built-in self-test using March-like algorithms

Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded flash memories are growing rapidly as we enter the system-on-chip (SOC) era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. We propose improved March-like algorithms (i.e., March FT) for both bit-oriented and word-oriented flash memory; to cover the disturbance faults derived from the IEEE 1005 Standard, as well as conventional faults. A novel flash memory fault simulator is used to analyze and generate the test algorithms. In addition, we present BIST designs for two industrial flash memories. The area overhead is only about 3% for a medium-sized flash memory.

RAMSES-FT: a fault simulator for flash memory testing and diagnostics

In this paper we present a fault simulator for flash memory testing and diagnostics, called RAMSES-FT. The fault simulator is designed for easy inclusion of new fault models by adding their fault descriptors without modifying the simulation engine. The flash memory fault models are discussed, based on the failures defined in the IEEE 1005 Standard. Both the NOR-type and NAND-type flash memory architectures are covered. Our flash memory fault simulator uses a parallel simulation strategy to reduce the simulation time complexity from O(N/sup 3/) to O(N/sup 2/), where N is the number of cells. With the proposed scaling method for March tests, the simulation time complexity is further reduced to O(W/sup 2/), where W is the word width of the memory. The fault simulator supports March algorithms as well as single memory operations, covering most of the flash memory tests. With RAMSES-FT we have developed a diagnostic algorithm that can distinguish the target flash memory faults.

Diagonal test and diagnostic schemes for flash memories

Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices. Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long test time, which in turn lead to high test cost. In this paper we propose a new diagonal test algorithm for flash memory that effectively reduces the test time without sacrificing the fault coverage. Both disturb faults and conventional RAM faults are covered. A diagnostic algorithm is also presented, which can distinguish among all the disturb faults and most of the conventional RAM faults. Finally, a built-in self-diagnosis (BISD) scheme is proposed. The BISD circuit implements our algorithms and user-defined ones, and its area overhead is low, e.g., it contains only about 2,551 gates (2-3%) for a 2 Mb flash memory. The test time by our diagonal test is reduced by about 42.69% as compared with the best March-like algorithm reported so far.

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

Automatic generation of memory built-in self-test cores for system-on-chip

Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.

A network security processor design based on an integrated SOC design and test platform

In this paper we present a generic network security processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, design-for-testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18 mum CMOS technology. The chip area is 5 mm times 5 mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80 MHz. The best performance of the crypto-engines is 1.025 Gbps for AES, 1.652 Mbps for RSA, 125.9/157.65 Mbps for HMAC-SHA1/MD5, and 2.56 Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability

An Enhanced EDAC Methodology for Low Power PSRAM

As feature size keeps shrinking, how to maintain the reliability becomes an important issue in IC production, especially for high density memory circuits. Error detection and correction (EDAC) schemes have been widely used for memory circuits for this purpose, but ordinary EDAC schemes are not suitable for memories with long codewords. The demand for low-power memory is increasing due to the growth in portable electronics markets. Power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve the above two issues, we propose a parallel encoding and decoding EDAC scheme, which can be used on memories with long codewords. Targeting refresh power reduction, we have implemented our scheme on an industrial pseudo SRAM (PSRAM), and have completed experiments. The major hardware penalty is the parity overhead that is 1/9, and the longest delay of our circuit is 3.6ns for the PSRAM fabricated by a 0.11mum CMOS technology. With respect to the 70ns access time of the PSRAM, the proposed EDAC scheme can be integrated with the read/write operations without increasing the latency. Experimental results show that the refresh time can be extended greatly, without sacrificing reliability

Scalable Security Processor Design and Its Implementation

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT (design for test) platform is also implemented for the design-test integration. The security processor has been fabricated (using UMC 0.18mum CMOS technology) and measured. The core area is 3.899mm times 2.296mm (525K gates approximately) and the operating clock rate is 66MHz