Kuo-Liang Cheng

March-based RAM diagnosis algorithms for stuck-at and coupling faults

Diagnosis technique plays a key role during the rapid development of the semiconductor memories, for catching the design and manufacturing failures and improving the overall yield and quality. Investigation on efficient diagnosis algorithms is very important due to the expensive and complex fault/failure analysis process. We propose March-based RAM diagnosis algorithms which not only locate faulty cells but also identify their types. The diagnosis complexity is O(17N) and O((17+10B)N) for bit-oriented and word-oriented diagnosis algorithms, respectively, where N represents the address number and B is the data width. Using the proposed algorithms, stuck at faults, state coupling faults, idempotent coupling faults and inversion coupling faults can be distinguished. Furthermore, the coupled and coupling cells can be located in the memory array. Our word-oriented diagnosis algorithm can distinguish all of the inter-word and intra-word coupling faults, and locate the coupling cells of the intra-word inversion and idempotent coupling faults. With additional 2B-1 operations, the algorithm can further locate the intra-word state coupling faults. With improved diagnostic resolution and test time, the proposed algorithms facilitate the development and manufacturing of semiconductor memories.

Flash memory built-in self-test using March-like algorithms

Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded flash memories are growing rapidly as we enter the system-on-chip (SOC) era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. We propose improved March-like algorithms (i.e., March FT) for both bit-oriented and word-oriented flash memory; to cover the disturbance faults derived from the IEEE 1005 Standard, as well as conventional faults. A novel flash memory fault simulator is used to analyze and generate the test algorithms. In addition, we present BIST designs for two industrial flash memories. The area overhead is only about 3% for a medium-sized flash memory.

Simulation-based test algorithm generation for random access memories

Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.

RAMSES-FT: a fault simulator for flash memory testing and diagnostics

In this paper we present a fault simulator for flash memory testing and diagnostics, called RAMSES-FT. The fault simulator is designed for easy inclusion of new fault models by adding their fault descriptors without modifying the simulation engine. The flash memory fault models are discussed, based on the failures defined in the IEEE 1005 Standard. Both the NOR-type and NAND-type flash memory architectures are covered. Our flash memory fault simulator uses a parallel simulation strategy to reduce the simulation time complexity from O(N/sup 3/) to O(N/sup 2/), where N is the number of cells. With the proposed scaling method for March tests, the simulation time complexity is further reduced to O(W/sup 2/), where W is the word width of the memory. The fault simulator supports March algorithms as well as single memory operations, covering most of the flash memory tests. With RAMSES-FT we have developed a diagnostic algorithm that can distinguish the target flash memory faults.

Fault simulation and test algorithm generation for random access memories

The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories

The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are March based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground March algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports March algorithms, including the proposed multibackground one.

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

Test scheduling of BISTed memory cores for SoC

The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic exhaustive search finds optimal results for large memory cores, while a heuristic ordering with simulated annealing further handles a large amount of smaller memory cores. On the average, the results are within 1% difference of the optimal solution for the cases of 200 memory cores.

Simulation-based test algorithm generation and port scheduling for multi-port memories

The paper presents a simulation-based test algorithm generation and test scheduling methodology for multi-port memories. The purpose is to minimize the testing time while keeping the test algorithm in a simple and regular format for easy test generation, fault diagnosis, and built-in self-test (BIST) circuit implementation. Conventional functional fault models are used to generate tests covering most defects. In addition, multi-port specific defects are covered using structural fault models. Port-scheduling is introduced to take advantage of the inherent parallelism among different ports. Experimental results for commonly used multi-port memories, including dual-port, four-port, and

Fault pattern oriented defect diagnosis for memories

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