Jennifer Kitchen

Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters

A combined linear and Δ-modulated switched-mode PA supply modulator for polar transmitters is designed in a 0.25μm CMOS process. The modulator follows the input envelope and achieves 20dB output DR, a maximum efficiency of 75.5%, and 75dB SNDR for envelope signals up to 4MHz occupied RF BW. For a 1625kb/s 8PSK RF input at 900MHz, polar modulation of a GSM-900 PA provides 10dB ACPR improvement.

Combined Linear and

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulators noise-shaping characteristic, linear regulators power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signals envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.

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This paper summarizes the advantages of PA linearization via polar modulation and illustrates the necessity for high-performance supply modulators in polar transmitters. Two potential modulator solutions are introduced; both having between 4 MHz and 20 MHz occupied RF bandwidth and more than 65 dB SFDR. These modulators process envelope information for 1625 kb/s 8PSK and CDMA IS95 applications in polar PA architectures. The presented circuits and signal processing techniques can be generalized for future modulator designs.

-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

We propose a self-test method for zero-IF radio frequency transceivers using primarily loopback, aided by a small built-in self-test (BIST) circuitry, to determine critical performance parameters, such as I/Q imbalance and nonlinearity coefficients. The transceiver is placed in the loopback mode by couplers, specifically designed to be asymmetric with respect to the primary path and the BIST path. The loopback path is also designed to include two traces with slightly different delays to enable parameter deembedding. Transceiver parameters are analytically computed using baseband I and Q signals over two frames, each of which is 200 μs in duration. Overall, measurement time is <;10 ms, including computation time. In addition to loopback hardware support and the associated parameter deembedding methodology, we propose a complimentary BIST circuit to measure the transmitter (TX) gain. The measured parameters can be used for predistortion or postdistortion to calibrate the transceiver, both at production time and in the field. Both simulation and hardware measurement results show that the proposed method can determine the target performance parameters with adequate accuracy for digital calibration. Measurement and the subsequent calibration are shown to reduce TX error vector magnitude more than fivefold, even for significantly impaired systems.

Supply modulators for RF polar transmitters

An RF Phased array can steer the direction of the beam electronically and it brings about benefits in terms of signal to noise ratio (SNR) and directivity. However, testing the phased array generally requires expensive and high performance RF equipment. This increases production test cost and hampers in-field calibration. We present a low-cost, self-compensating Built-In Self-test (BIST) and calibration solution for RF phased arrays. In our proposed method, we apply a sinusoidal test signal with unknown amplitude to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. The BIST circuits are designed and post layout simulations are performed with within-die and die-to-die process variations. Simulations confirm that the BIST circuit provides very accurate results without having to know sinusoidal signal amplitudes or the relation between them. Furthermore, a prototype four-element phased-array PCB was designed and fabricated for verifying our proposed method. With the proposed method, the phase difference between elements can be measured and calibrated with less than 1° error, which would allow for self-monitoring in 6-bit phased array applications.

Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers

RF Built-in-Self-Test requires generation and analysis of high frequency signals on-chip, which usually involves complex circuitry. Generally a high frequency to low frequency conversion, such as a peak or amplitude detector, is employed to analyze the output of the device under test (DUT). However, this conversion circuit is subject to similar process variations as the DUT, which has to be included in the measurement process. Moreover, despite affecting the accuracy of the entire measurement, the input generation for RF BIST is sparsely discussed. While relative measurements, such as gain, can be made without knowing the input signal attributes, other parameters, such as output power, IIP3, or IIP5 require absolute measurements, hence the knowledge of the input signal amplitude. In this paper, we propose a technique for on-chip amplitude measurement that is independent of process variations. The approach relies on on-chip generation of a square wave using an RF limiter with two different amplitudes. Using these two input signals and mathematical modeling, we extract the amplitude at the output of the DUT with high accuracy. The circuits for the BIST have been designed and simulated at the transistor level, including process variations. The concept of the proposed measurement technique is demonstrated in hardware using off-the-shelf components.

A self-compensating built-in self-test solution for RF phased array mismatch

Failure due to aging mechanisms in CMOS devices is an important concern of RF circuits. Lifetime of analog/RF circuits is defined as the point where at least one specification will fail due to aging effects. In this brief, we present a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices and inductors at design time (presilicon). We identify reliability hotspots and concentrate on these circuit components to enhance the lifetime with low area and no performance impact.

Robust amplitude measurement for RF BIST applications

This paper describes a 6-bit programmable True Time Delay (TTD) system for 1-12GHz applications. The minimum delay resolution is 20ps, and maximum delay is 1.35ns, thus making it suitable for phased array antenna and imaging applications. The programmable TTD system simulation results show better than 9dB of input and output return loss across the entire frequency range. As a proof of concept, a 40ps unit cell delay is realized in the GlobalFoundries (GF) 180nm CMOS technology. The fabricated unit cell has less than 2.5dB insertion loss and better than 9dB return loss within the entire frequency range. The fabricated TTD unit cell occupies 0.3 X 0.35mm2.

Design-Time Reliability Enhancement Using Hotspot Identification for RF Circuits

Wireless Revolution V.2 in the form of Internet of Things (IoT) necessitates development of RF on rapidly evolving manufacturing processes using a small team of engineers. These processing nodes are tuned for digital performance and typically present with higher process variations. Manufactured RF devices either need to include larger margins to guarantee performance or be tuned post-manufacture to recover the performance. In this paper, we present a set of design principles for RF devices that can be adapted post-production for specific needs of the target application. Post-production tuning lifts the design burden from engineering efforts to measurement and calibration at the production test time.

Wide band programmable true time delay block for phased array antenna applications

This work presents a transformer-coupled class D switched-mode power amplifier using GaN-on-Si. An aggressive time-domain compatible, scalable, Angelov device model is used to accurately predict transient switched-mode device behavior. Simulation and measurement results report the GaN power devices intrinsic device efficiency to be 62% when operating as a switch at 2.25Gb/s. The 2-transistor PA topology demonstrates 29.5% efficiency at maximum power. When driven with a silicon-based sigma-delta RF modulator, the PA processes a single-carrier WCDMA waveform with -40.4dBc ACPR1.