Sayfe Kiaei

Equalization for discrete multitone transceivers to maximize bit rate

In a discrete multitone receiver, a time-domain equalizer (TEQ) reduces the intersymbol interference (ISI) by shortening the effective duration of the channel impulse response. Current TEQ design methods such as the minimum mean-squared error (MMSE), maximum shortening SNR (MSSNR), and maximum geometric SNR (MGSNR) do not directly maximize bit rate. We develop two TEQ design methods to maximize the bit rate. First, we partition an equalized multicarrier channel into its equivalent signal, noise, and ISI paths to develop a new subchannel SNR definition. Then, we derive a nonlinear function of TEQ taps that measures the bit rate, which the proposed maximum bit rate (MBR) method optimizes. We also propose a minimum-ISI method that generalizes the MSSNR method by weighting the ISI in the frequency domain to obtain higher performance. The minimum-ISI method is amenable to real-time implementation on a fixed-point digital signal processor. Based on simulations using eight different carrier-serving-area loop channels, (1) the proposed methods yield higher bit rates than MMSE, MGSNR, and MSSNR methods; (2) the proposed methods give three-tap TEQs with higher bit rates than 17-tap MMSE, MGSNR, and MSSNR TEQs; (3) the proposed MBR method achieves the channel capacity (as computed by the matched filter bound using the proposed subchannel SNR model) with a five-tap TEQ; and (4) the proposed minimum-ISI method achieves the bit rate of the optimal MBR method.

Class of cyclic-based estimators for frequency-offset estimation of OFDM systems

We present a new class of blind cyclic-based estimators for carrier frequency-offset and symbol-timing error estimation of orthogonal frequency-division multiplexing (OFDM) systems. The proposed approach exploits the properties of the cyclic prefix subset to reveal the synchronization parameters in the likelihood function of the received vector. A new likelihood function for the joint timing and frequency-offset estimation is derived, which globally characterizes the estimation problem. The resulting probabilistic measure is used to develop three classes of unbiased estimators, namely, maximum-likelihood, minimum variance unbiased, and moment estimator. In comparison to the previously proposed methods, the proposed estimators in this study are computationally and statistically efficient, which makes the estimators more attractive for real-time applications. The performance of the estimators is assessed by simulation for an OFDM system.

Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs

CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing ( Delta V/sub L/ approximately=0.2 V/sub dd/) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2- mu m CMOS process, and simulated results with a standard 1- mu m process are used to compare the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies. >

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.

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Mobile communication systems require highly efficient, linear, and integrated power amplifiers. This paper reports the results of a monolithic envelope following system implemented in a 0.18 /spl mu/m SiGe BiCMOS process technology. The monolithic envelope following system consists of a synchronous buck DC-DC converter, which is integrated with and provides the power supply for a 900 MHz power amplifier while tracking the envelope of the RF input signal.

m SiGe Process

A combined linear and Δ-modulated switched-mode PA supply modulator for polar transmitters is designed in a 0.25μm CMOS process. The modulator follows the input envelope and achieves 20dB output DR, a maximum efficiency of 75.5%, and 75dB SNDR for envelope signals up to 4MHz occupied RF BW. For a 1625kb/s 8PSK RF input at 900MHz, polar modulation of a GSM-900 PA provides 10dB ACPR improvement.

Monolithic supply modulated RF power amplifier and DC-DC power converter IC

A fully differential source-coupled logic technique intended for mixed-mode applications has been developed. Implemented in 2- mu m CMOS technology with a 5.0-V supply, the minimum propagation delay is about 750 ps with an 800-mV logic swing. Power supply current spikes are reduced by about two orders of magnitude compared to conventional static CMOS logic.<<ETX>>

Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters

The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2- mu m p-well CMOS process. With V/sub dd/=5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ). >

CMOS source-coupled logic for mixed-mode VLSI

A fully integrated 0.18mum SiGe synchronous buck DC/DC converter with an on-chip LC output filter supporting a maximum output current of 200mA and efficiency of 64% is presented. The converter utilizes a 10mum-thick electroplated copper layer for integrated inductors and gate capacitors. High switching frequency of 45MHz, multi-phase interleaved operation, and fast hysteretic control reduces the filter inductor and capacitor sizes by two orders of magnitude enabling a fully integrated converter

Synthesis techniques for CMOS folded source-coupled logic circuits

A combined class-AB and switch-mode regulator based supply modulator with a master-slave architecture achieving wide bandwidth and low ripple is presented. Low frequency content of the envelope waveform is provided by a synchronous-rectifier based switch-mode power supply while high frequency content is provided by a rail-to-rail class-AB amplifier. A wide range, low loss output current sensing circuit is used at the class-AB amplifier output, canceling the ripple due to switch-mode power supply and extending overall modulator bandwidth. The proposed regulator is designed and fabricated on a 0.35 mum CMOS process. The combined regulator achieves a maximum efficiency of 82% and an IMD3 of 65 dBc at 10 MHz for 16 dBm output power. The regulator achieves a frequency range up to 10 MHz with less than 0.2% envelope tracking error, making this PA regulator suitable for CDMA applications.