Jens Paul

CPI challenges to BEOL at 28nm node and beyond

We address package-induced degradation of BEOL interconnects and approaches for recovery. For dielectrics, we cover process options and position in stack for ULK films and how these lead to differences in strength. Experiments were designed to cross-compare multiple methods to test susceptibility of BEOL interconnect to CPI damage. We also address how Chip Package Interaction changes as BEOL features and layout evolve.

Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application

Fhis paper discusses the extensive development work carried out by GLOBALFOUNDRIES to mitigate chip-package interaction (CPI) risks for the silicon Backend of Line (BEOL) during IC package assembly. Particularly, material property data for different ultra low k (ULK) materials, CPI qualification results and key findings made during the technology development are discussed. Newly developed test and modeling methods to expedite technology learning are also described in detail.

TSV integration on 20nm logic Si: 3D assembly and reliability results

Each new technology node brings new design and technology challenges making it harder to maintain Moores law in a cost effective way. Maintaining cost effectiveness is becoming a major challenge for IDMs, fabless companies and foundries. 3D/2.5D technologies offer some unique advantages over traditional scaling such as higher power efficiency, higher bandwidth and heterogeneous integration which can arguably lower design complexity and manufacturing cost. While advantages of 3D ICs are well known, adoption of this technology has been shifting out due to several technological challenges and manufacturing supply chain concerns. In this paper, 3D packages are realized by stacking mechanical Wide IO memory onto a 20nm low power mobile logic die with through silicon vias (TSVs). This architecture is very promising for mobile application as it can provide lower power consumption, higher bandwidth and faster communication between memory and logic with a smaller form factor. Various technical challenges that were addressed while building a 3D package along with its process and reliability results, both wafer level and package level, are discussed in this paper.

CPI assessment using a novel characterization technique based on bump-assisted scratch-indentation testing

Integration of compliant and brittle ultralow-k (ULK) interlayer dielectric (ILD) materials in advanced backend-of-line (BEOL) layer stacks requires a careful characterization of the mechanical stability of the BEOL stack to assure reliability during chip packaging and under field condition. We present a novel experimental technique which applies normal and shear forces on Cu pillars to test the stability of BEOL layer stacks beneath individual pillars. Critical forces and displacements are recorded with high sensitivity. The test directly verifies if the BEOL withstands the applied stress levels or if mechanical failure occurs.

Advanced chip package interaction qualification for critical stacks in combination with Cu pillar interconnect technology

For mobile applications, advanced silicon technology nodes are using Back End Of Line (BEOL) stacks with Ultra Low-k (ULK) materials. Employing these ULK materials in combination with advanced Flip Chip (FC) packages requires a profound understanding of the chip package interaction (CPI). To match high I/O and reduced pitch requirements, Cu pillars are widely used as first level interconnect technology [MCC15, KAU15, KUE12 LEE013, RYA12]. In general, Cu pillars are known to increase the stress in the BEOL stacks compared to conventional SnAg interconnects. More viscoplastic deformation occurs in SnAg interconnects and reduces the stress in the BEOL. Therefore, the combination of Cu pillars and aggressive low cost, high performance BEOL stacks with ULK materials requires a systematic concept for the CPI qualification. This includes window studies and margin tests and requires a close collaboration of silicon foundry and the assembly facility.

Chip package interaction with Cu Pillar interconnects - systematic study of key factors impacting the qualification

Advanced silicon technology nodes are using backend of line (BEOL) stacks consisting of ultra low-k (ULK) materials. ULK materials in combination with Flip Chip (FC) packages and Cu pillar first level interconnects require a chip package interaction (CPI) characterization strategy. Package level tests are needed to account for the thermal mismatch or warpage induced stress between the silicon die and the polymer substrate.

Mechanical reliability assessment of 28nm Back End of Line (BEoL) stack using finite element analysis and validation

In order to address the Chip-Package Interaction (CPI) challenges at an early stage of the product development, GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in Backend of Line (BEoL). This paper elaborates the methodology involved in developing a single bump simulation model to assess failure risk under mechanical loading. The paper also highlights the FE models validation by comparing the simulation results to the experimental test data.

Microprobing the mechanical effects of varying dielectric porosity in advanced interconnect structures

Chip-package interaction has become a major concern due to increasingly porous low-K dielectrics. During the packaging process, shear stresses are exerted on fragile interconnect structures. We use a microprobe metrology system to experimentally measure how interconnect stacks with different dielectric porosities behave under various shear loading conditions and a wide range of temperatures.