Jeong Dong Choe

Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.

A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.

Characteristics of body-tied triple-gate pMOSFETs

Body-tied triple-gate pMOSFETs were fabricated using bulk Si wafers and characterized. Process steps to implement the devices are explained briefly. Device characteristics of the triple-gate pMOSFETs were compared with those of the conventional planar channel device. While maintaining low off-leakage currents and threshold voltages similar to those of planar pMOSFETs in the parallel arrayed 30 000 transistors, the body-tied triple-gate MOSFETs showed about 74 mV/dec of subthreshold swing (92 mV/dec for conventional devices) and a drain-induced barrier lowering of 34 mV/V (92 mV/V for conventional devices). It was also addressed that I/sub SUB//I/sub D/ of the body-tied triple-gate is lower than that of the planar channel device.

Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process

By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.

Fabrication and characteristics of P-channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure

A p-channel silicon-oxide-nitride-oxide-silicon (SONOS) flash memory device based on bulk fin shaped field effect transistor (FinFET) structure was fabricated and characterized as a highly scalable device structure. Key process steps were explained in detail and electrical characteristics were measured. The threshold voltage shift (ΔVth) was checked in the proposed device with the source/drain floating and grounded. This result means that the proposed device structure can be applicable to NAND and NOR flash memories. In this structure, program/erase times can be controlled by fin body width, which is the unique parameter of FinFET structure. In the endurance test, about 1.3V of the ΔVth was kept until 104P∕Ecycles. The ΔVth of the proposed flash memory device was extrapolated to about 0.5V after 10y retention. The ΔVth with crystal orientation of the side-channel also was checked.

Fin width scaling criteria of body-tied FinFET in sub-50 nm regime

For better subthreshold swing (SS) and drain induced barrier lowering (DIBL) of FinFETs, the fin width is a more important parameter than the physical gate length. And it should be very thin and fully depleted. In this article, we introduce the fabrication of body-tied FinFETs with various fin widths, fabricated on bulk Si instead of SOI wafer, and propose a new gate length/fin width (L/sub g//W/sub fin/) criterion to get nearly ideal SS and DIBL for body-tied FinFETs. From experiments and simulations, it is proven that threshold voltage (V/sub th/) control is possible even under a 20 nm narrow fin width, and high performance FinFET operation is obtainable even under a 5 nm fin width.

Lateral integration of partially insulated and bulk MOSFETs using partial SOI process

We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.

The Vth controllability of 5nm body-tied CMOS FinFET

In this paper, we demonstrate a 5nm width body-tied CMOS finFET on bulk Si for the first time. Also the threshold voltage control of the 5nm finFET is shown by using channel and pocket doping profile optimization along the narrow active fin. The excellent performance of finFET such as an excellent subthreshold swing (SS), and drain induced barrier lowering (DIBL) characteristics were found. And the systemic analyses of electrical characteristics dependencies on the fin width were evaluated for various fin width (5 /spl sim/ 100nm).

Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions

The body-tied finFET (called OMEGA (Ω) metal oxide semiconductor field effect transistor (MOSFET)) exhibits positive characteristics as a future complementary metal oxide semiconductor (CMOS) device. The Ω MOSFETs have unique features such as high heat dissipation to the Si substrate, no floating body effect, and low defect density, while having the key advantages of the silicon-on-insulator (SOI)-based finFET characteristics. In order to increase the threshold voltages on both the Ω NMOSFET and the Ω PMOSFET while keeping the conventional gate electrodes (n+ polysilicon and p+ polysilicon gates for NMOSFET and PMOSFET, respectively), the device characteristics of the Ω MOSFETs have been characterized with halo ion implantation doses for the Ω NMOSFET and lightly doped drain (LDD) doses for the Ω PMOSFET. It was shown that the VTH adjustment could be partially achieved.