Tai-su Park

Streamline upwind numerical simulation of two-dimensional confined impinging slot jets

Abstract In the present paper, flow and heat transfer characteristics of confined impinging slot jets have been numerically investigated using a SIMPLE-based segregated streamline upwind Petrov–Galerkin finite element method. For laminar jets, it is shown that the skin friction coefficient approaches the grid-independent Galerkin solution and that the present simulation induces negligible false diffusion in the flow field. For turbulent jets, the k–ω turbulence model is adopted. The streamwise mean velocity and the heat transfer coefficient respectively agree very well with existing experimental data within limited ranges of parameters.

Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.

A 40 nm Body-Tied FinFET (OMEGA MOSFET) Using Bulk Si Wafer

Abstract A new body-tied FinFET is proposed and fabricated on bulk Si wafer instead of SOI wafer. Three-dimensional device simulations show the characteristics of the proposed device and show that it can be implemented without deteriorating short channel effect. An active fin width of 25– 40 nm and a gate length of 40 nm were realized by using sidewall spacer technology.

Characteristics of body-tied triple-gate pMOSFETs

Body-tied triple-gate pMOSFETs were fabricated using bulk Si wafers and characterized. Process steps to implement the devices are explained briefly. Device characteristics of the triple-gate pMOSFETs were compared with those of the conventional planar channel device. While maintaining low off-leakage currents and threshold voltages similar to those of planar pMOSFETs in the parallel arrayed 30 000 transistors, the body-tied triple-gate MOSFETs showed about 74 mV/dec of subthreshold swing (92 mV/dec for conventional devices) and a drain-induced barrier lowering of 34 mV/V (92 mV/V for conventional devices). It was also addressed that I/sub SUB//I/sub D/ of the body-tied triple-gate is lower than that of the planar channel device.

Fabrication and characteristics of P-channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure

A p-channel silicon-oxide-nitride-oxide-silicon (SONOS) flash memory device based on bulk fin shaped field effect transistor (FinFET) structure was fabricated and characterized as a highly scalable device structure. Key process steps were explained in detail and electrical characteristics were measured. The threshold voltage shift (ΔVth) was checked in the proposed device with the source/drain floating and grounded. This result means that the proposed device structure can be applicable to NAND and NOR flash memories. In this structure, program/erase times can be controlled by fin body width, which is the unique parameter of FinFET structure. In the endurance test, about 1.3V of the ΔVth was kept until 104P∕Ecycles. The ΔVth of the proposed flash memory device was extrapolated to about 0.5V after 10y retention. The ΔVth with crystal orientation of the side-channel also was checked.

Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

Plasma doping and laser annealing are successfully integrated into the conventional p-metal–oxide–silicon field effect transistor (PMOSFET) process to form ultra shallow junction (USJ). Comparing with the conventional combination of ion implantations and rapid thermal annealing (RTA), junction depth (XJ) and sheet resistance (RS) are reduced. Also, significant improvement of the short channel effects without the degradation of on-current is observed.

Si adatom diffusion on Si (100) surface in selective epitaxial growth of Si

The growth temperature dependence of Si adatom diffusion on Si (100) surface was systematically investigated in a cold wall ultrahigh vacuum chemical vapor deposition system. Si epitaxial layers were selectively grown on local oxidation of silicon patterned Si substrates. By cross-sectional transmission electron microscopy analysis, the increase in Si growth rate on the Si (100) surface near the edge of (311) facet was observed at various growth temperatures. This can be understood as a consequence of the mass transport from the sidewall (311) facet to the top (100) surface. Based on a simple diffusion model, the surface diffusion lengths of Si adatoms along the [110] direction were estimated to be about 70, 140, and 200 nm at 550, 600, and 650 °C, respectively. The calculated activation energy of 1.4 eV for diffusion of Si adatoms from the temperature dependence of the diffusion length was relatively higher than those in previous reports obtained under ultrahigh vacuum environment. This difference was discussed in terms of the discrepancy in the surface states by hydrogen adsorption on the Si surface.

Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

Device design using body-tied fin field effect transistor (bulk FinFET) was considered for the application to 50 nm DRAM technology. We concentrated on the device characteristics such as threshold voltage (Vth), off-state leakage current (Ioff), subthreshold swing (S.S), and drain induced barrier lowering (DIBL) by controlling lightly doped drain (LDD) profile of the bulk FinFET. Bulk FinFETs with 0 to 3 nm non-overlap between source/drain (S/D) to gate electrode show lower Ioff, S.S, and DIBL than those with an overlap while maintaining reasonable threshold voltage. We also compared characteristics of the triple gate bulk FinFET with those of the double gate bulk FinFET. Finally, electrical characteristics with LDD doping profile, S/D to gate overlap length, top gate oxide thickness, body doping concentration, fin top doping concentration, and doping profile from the edge to the center of the fin body are also compared.

Negative bias temperature instability(NBTI) of bulk FinFETs

We investigated the negative bias temperature instability (NBTI) of bulk FinFETs for the first time. Since the bulk FinFET has a body terminal, it is more flexible in studying the NBTI characteristics than the SOI FinFET (no body terminal). The dependence of NBTI on the back bias is smaller in a 100 nm bulk FinFET with a fin width of 30 nm than in conventional planar channel devices. The bulk FinFET with a side surface orientation of (100) showed better NBTI than the device with an orientation of [110]. The fin width was shown to have little impact on NBTI in the bulk FinFET. Moreover, the device with longer channel showed less degradation.

Body-tied double-gate SONOS flash (omega flash) memory device built on bulk Si wafer

In this paper, for the first time, a body-tied double-gate SONOS flash memory device using bulk Si wafer is proposed. Brief fabrication steps and measured characteristics are presented.