Yoo-Hyon Kim

CHAMPS (chemical-mechanical planarization simulator)

Simulation of chemical-mechanical polishing is important because the chip-level planarity and wafer-level uniformity dependent on many dynamic factors are difficult to control. CHAMPS (chemical mechanical planarization simulator) has been developed for predicting and optimizing the thickness distribution after the CMP process using the chip level pattern density and an elastic spring model including equipment parameters. In this work, the results of CMP simulation are shown to agree well with the measured data. This simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve planarity and uniformity.

An efficient rule-based OPC approach using a DRC tool for 0.18 /spl mu/m ASIC

The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASICs. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.

A fast lithography verification framework for litho-friendly layout design

The increase in pattern complexity due to optical proximity correction (OPC), the tight requirements for critical dimension (CD) control and the difficulties in defect inspections make IC manufacture more expensive. To alleviate the high cost, manufacturing requirements must be handled at the design stage to improve the quality and yield of ICs. We demonstrate the extraction of critical areas for detecting failures and a new lithography simulation method for full-chip level optical proximity corrected layout. The methodology has been used in our mask verification process that is called litho-friendly layout (LFL). For the critical area extraction, we present three approaches using process window, normalized image log-slope (NILS) and edge placement error (EPE). For full-chip level simulation, we introduce an automatic calibration method for simulation process parameters, a mask decomposition method and a selective simulation method. The verification process includes lithography process simulation, print-image based LVS (layout vs. schematic) and DRC (design rule check). We also demonstrate that LFL can provide guidelines for better OPC of sub-80 nm processes.

CMP profile simulation using an elastic model based on nonlinear contact analysis

Recently, simulation of Chemical Mechanical Polishing (CMP) is becoming more important because planarity and uniformity which are dependent on many dynamic factors are difficult to control. In this paper, a profile simulation environment based on the linear elastic material and nonlinear contact analysis that considers equipment parameters, such as pad hardness, thickness and down pressure is presented. In transient CMP simulation using the elastic model, the contact stress on the wafer surface is the dominant factor in polishing rate during the CMP process. The profiles of CMP simulation agree well with the measured data. This simulation can be used to optimize the CMP process and to generate design rules for filling dummy patterns which are used to improve planarity.

Practical approach to control the full-chip-level gate CD in DUV lithography

A practical method to control the full chip level gate CD of a logic device with a 0.28 micrometer minimum design rule in DUV lithography is evaluated using an automatic optical proximity correction (OPC) software with empirical modeling. The CD variation on a chip results from the proximity and uniformity CD errors. The proximity error occupying more than 40% of total CD variation is caused by the pattern geometry, resist process, and mask CD error. In this paper, the OPC has been applied to line width narrowing and line-end shortening. The line-end shortening has been corrected by only the line- end extension instead of adding serifs which can be mistaken for defects during mask inspection. From this work, 43% reduction of the CD variation induced by proximity in the 3(sigma) standard deviation has been achieved at the 14 nm correction unit. Furthermore, the focus margin of 1.2 micrometer after OPC has been guaranteed. The results of line- end correction show that the line-end extension correction is sufficient to correct the overlap mismatching between the active and gate layers.

Evaluating the accuracy of a calibrated rigorous physical resist model under various process and illumination conditions

If RET selection by simulation is to be successful for the deep sub-wavelength technologies of today, then the predictions of the simulator must be quantitatively accurate over the parameter space of interest. The Rigorous Physical resist Model (RPM) within PROLITH and Lithoware is separable from the illumination conditions and the reflection behavior of the wafer stack, and thus should be an excellent candidate for such projects. In this work, the RPM is calibrated for a commercially available ArF photoresist using topdown CD-SEM data, including focus-exposure matrices and CD vs. mask pitch data, under fixed process conditions. It will be shown that this RPM is able to predict the performance of line, trench and contact features, with quantitative accuracy, under different numerical aperture and illumination conditions, even when the wafer stack is altered significantly. The stack alterations include resist thickness change, the presence or absence of an immersion topcoat, substitution of different underlying substrate materials and the use of a single or double layer anti-reflection coating. The resist model accurately describes both the experimental calibration data and two separate experimental validation datasets. The RMS error seen in the extrapolative predictions is comparable to that observed between the model and the original calibration dataset.

Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL) [1] is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.

Simulation-based critical-area extraction and litho-friendly layout design for low-k 1 lithography

As the lithography process approaches to the low k1 regime, the layout designers are forced to design the litho-friendly layout, which considers the process margin and mask error enhancement factor (MEEF). In addition, the lithography engineers are also impelled to optimize the optical proximity correction (OPC) rules at the full-chip level to eliminate the failures of the printed image on the wafer. Therefore, we have newly developed the simulation-based critical area extraction (CAE) and litho-friendly layout (LFL) design methodology based on the layout editor environment to design the litho-friendly layout and optimize the OPC rules. In this methodology, the critical areas of the full-chip level post-OPC layout, which have the lower process margin and larger critical dimension (CD) variation, are automatically extracted by evaluating the focus-exposure window, normalized image log-slope (NILS) and edge placement error (EPE). The extracted critical areas are sorted according to their causes of failures (i.e., notching, bridging, line-end shortening and larger CD variation, etc.). In order to maximize the process margin and minimize the MEEF at the full-chip level, layout designers and lithography engineers modify the original layout and optimize the OPC rules of the sorted critical areas based on the lithography simulator. The simulator uses the mask decomposition and selective simulation method to reduce the simulation time at the full-chip level. For the convenient CAE, process margin evaluation and layout optimization, the CAE function and lithography simulator are combined with the layout editor environment. Applying this methodology to the memory device of sub-90nm design rule, we have validated that our methodology can capture the pattern failures at the full-chip level and optimize both the original layout and OPC rules of those areas.

Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node

As semiconductor devices are scaled down to the sub-100nm node, the fine control of ACLV (across-chip line-width variation) to improve the performance of chips and the expansion of the process window to enhance yield are required. One of the techniques reducing ACLV is MPPC (model-based process proximity correction). However, it increases pattern complexity and does not guarantee enough process windows. Therefore, we propose a HPPC (hybrid PPC) methodology combining RPPC (rule-based PPC) and MPPC, which correct the gate on active by MPPC for device performance and the field gate by RPPC for process window. In addition, we optimize SRAF (sub-resolution assist feature) design to improve process windows further at the full chip level and apply the multi-step correction, which corrects optical and etch proximity effects separately to minimize ACLV. As the result of the application to the 90nm logic gate, we achieve over 0.3um DOF (depth of focus) and the line-width variation within ±5% of the target CD (critical dimension).

Optical proximity correction considering mask manufacturability and its application to 0.25-μm DRAM for enhanced device performance

A practical optical proximity correction (OPC) method is introduced and applied to 0.25 micrometers DRAM process in order to reduce the gate critical dimension (CD) variations across the exposure field. A variable threshold model is made and evaluated to enhance the model accuracy. This model takes maximum 2X computation time compared with the constant threshold model. The proposed OPC methodology considering both process effects and mask manufacturability simultaneously is discussed in view of the gate line CD variation. The correction segments of a pattern are optimized considering mask manufacturability. Patterns with jog sizes larger than 0.4 micrometers are inspect able with KLA35UV. The OPC results exhibited 60 percent reduction of gate CD variation, 90 percent matching of mean-to-target CD, and 15 percent improvement of circuit performance.