Jeong-Uk Han

Electrical characterization of contact level PVC (Passive Voltage Contrast) test using a nanoprober

PVC (Passive Voltage Contrast) fault isolation method by using a SEM (Scanning Electron Microscope) has been widely used for isolating the defective mc (metal contact) in the CMOS logic SRAM bit cell array. The low power (LP) processed sram cells are easy to charging under PVC test and it helps isolating defective contacts in the cell. However, some device such as a high speed (HS) sram cell is hard to charging in PVC test by unknown reason. It makes difficulties for isolating defective contacts in the sram cell array. In this paper, our group analyzed the electrical current of each contact in sram cell using a nanoprobing technique and correlated it with PVC charged contact images, respectively. Also, the difference of PVC charging status between LP and HS SRAM are characterized electrically by using a nanoprober. The nanoprobing result indicates that a slight increasing a leakage current of about 10pA can abruptly change the charging brightness from dark to grey. Finally, we can found some clues for making grey contacts of HS SRAM using not only a nanoprobing but also a HRTEM (High Resolution Transmission Electron Microscope) image.

Both NOR and NAND Embedded Hybrid Flash for S-SIM Application Using 90 nm Process Technology

We have firstly demonstrated a hybrid flash including both NOR and NAND cell in a single chip using 90 nm logic technology for S-SIM (Super-Subscriber Identity Module) application. The memory sizes are 16 MB NAND and 768 kB NOR flash, respectively. The flash memory cells exhibited over 10 k-cycle endurance and 10-year retention for the successful smart card application.

Robust pad layout to improve wire bonding reliability

Different from the conventional study to improve the pad reliability against the peel-off, this study focuses on the probability that the peel-off could be originated from the perpendicular pushing down mechanical stress (PPMS) during the ball mounting process. Suggested in this paper are a new model which causes the peel-off and a new pad structure that overcomes the pad peel-off without any special procedures or changes in material or dimension. Three sets of layout patterns have been designed and fabricated in a 0.13 µm CMOS process. To assess the wire bonding quality, wire pulling tests (WPT) and evaluation of bonding power dependencies by means of wedge wire bonding are conducted. Additionally, FAMMOS simulator is adopted to verify the newly proposed pad structure.