Yong-kyu Lee

A Low Power Content Addressable Memory Using Low Swing Search Lines

This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. The 128 × 144 bit CAM chip was fabricated using a 0.18 μm CMOS process with VDD = 1.8 V. The CAM chip dissipates 2.82 fj/bit/search and consumes 8.7% of the power used by a conventional dynamic NOR-type CAM. It saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively. Its area is 1.14 mm2. Its maximum operating frequency is 210 MHz.

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions

In this article, we evaluated the structural merits of a partially insulated MOSFET (PiFET), for ultimate scaling of planar MOSFETs, through simulation and fabrication. The newly fabricated PiFET showed outstanding short channel effect (SCE) immunity and off-current characteristics over the conventional MOSFET, resulting from a self-induced halo region, self-limiting S/D shallow junction, and reduced junction area due to PiOX layer formation. Thus, the PiFET can be an attractive alternative for ultimate scaling of planar MOSFETs.

Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance

We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.

Practical Consideration of Both Endurance and Performance for Sub-90 nm Embedded Two Transistor Fowler?Nordheim Tunneling Flash Memory

Practical consideration about performance and endurance of two transistor Fowler–Nordheim tunneling (2T-FN) embedded flash cell has been suggested to expand its application not only for subscriber identity module (SIM) but also new various uses in smart-phone. We present practical 35% improvement on endurance characteristics (ΔVth) without any performance degradation.