Youngkook Ahn

5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity

A high-voltage-tolerant buck converter with a novel adaptive power transistor driver is proposed in this paper. In order to minimize the RON of the cascode power transistor, the proposed scheme uses optimized and separated driving voltages for bias of the pMOS and nMOS power transistors. This increases not only the conversion efficiency, but also the maximum allowable load current for the transistor driver with small layout size, when compared to the buck converter with the earlier scheme. The measurements show that when the supply voltage is 2.5 V and the load current is 150 mA, the efficiency of the buck converter with the earlier scheme is 82%, whereas the efficiency of the buck converter with the proposed scheme is 92%, showing a maximum improvement of 10%. The designed buck converter uses the 0.35- μm-thick gate oxide CMOS process, and at 2.5-5 V of voltage, can supply up to 380 mA of load current. The total chip size is 2.7 mm2.

A 50-MHz Fully Integrated Low-Swing Buck Converter Using Packaging Inductors

Implementation of on-chip passive elements and efficient regulation schemes are key aspects of fully integrated dc-dc converter design. This paper presents a 50-MHz fully integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also presents full-swing and low-swing gate drivers for efficient regulation of high-frequency switching converters. The low-swing driver uses the drop voltage of a diode-connected transistor and is applied in a fabricated converter to reduce the gate driving loss caused by the high switching operation. The proposed converter is designed and fabricated using a 0.13-μm 1-poly 6-metal CMOS process. The fully integrated buck converter achieves 68.7% and 76.8 % efficiency for 3.3 V/2.0 V and 2.5 V/1.8 V conversions, respectively, while providing a load current of 250 mA.

A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control

Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 μm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A.

DC-DC switching converter with positive and negative outputs for active-matrix LCD bias

A DC-DC switching converter chip is proposed to generate both positive and negative voltages for active-matrix LCD (AMLCD) bias. An inductive boost converter and two inverting charge pumps are integrated in a proposed chip by using a 0.5 ?m 5 V, 3.5 ?m 30 V CMOS process. A conventional scheme used to bias AMLCD employs a switching-boost converter with several off-chip components to generate the required positive and negative voltages. The circuit proposed in this study achieves high performance with a minimum number of off-chip components. Additionally, the proposed method is capable of generating a wide range of negative voltages by varying the reference voltage to supply optimised power for the AMLCD system. Because the supply voltage of the developed inverting charge pump is supplied by the output voltage of the boost converter through a linear regulator, the operations of switching-boost converter and inverting charge pump are independent and are without cross-regulation problems. The boost converter-s input power supply range is 2.8-5.5 V, the output voltage range is 10-20 V and the clock frequency is 780 kHz. The maximum efficiency is 84% with the input power supply at 5.5 V, an output voltage of 10 V and a load current of 100-mA. The integrated inverting charge pumps have two outputs that generate -2× and -4× the reference voltage. The overall core size is 2150 ?m × 2150 ?m.

A 93.5% efficiency, 400-mA current-mode dc-dc buck converter with watchdog functions

A current-mode dc-dc buck converter was implemented in a standard 0.35- m 1-poly 6-metal 3.3-V CMOS technology. This paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. The dc-dc converter systems can be protected from over-voltage, over-temperature, and over-current conditions. In addition to the protection from destructive conditions, a reversecurrent protection circuit is implemented to improve efficiency under light-load conditions. The maximum efficiency of the fabricated converter was 93.5%. The chip area is only 1.02 mm2.

1.5 MHz, 300 mA step-down switching regulator

A switching regulator yields high efficiency and provides a good current driving capability, making it appropriate as a DC-DC converter for mobile devices. The battery voltage can be converted into the operating voltage of the internal circuit. Furthermore, a negative feedback loop can be constructed to restrict change in dc voltage for a stable supply. A current-mode switching regulator adjusts the inductor current to stabilize the output voltage. The designed 1.5 MHz 300 mA step-down switching regulator is implemented in a standard 0.18-mum CMOS process.

Design of buck converter circuits operating in weak-inversion region

A 900-nA quiescent current buck converter is implemented in standard 0.25 mum CMOS technology. The controllers analog subblocks are designed to operate in weak-inversion region to reduce quiescent current. It also implements internal compensation circuit to minimize external passive components. In order to reduce the size of an on-chip capacitor, the Miller effect is utilized. The measurement results show the successful operation of the DC-DC converter in extremely low quiescent current.