Gregg J. Fokken

Description and evaluation of the FAST-Net smart pixel-based optical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Emerging multigigahertz digital and mixed-signal integrated circuits targeted for military applications: dependence on advanced electronic packaging to achieve full performance

A revolution is occurring in several device and integrated circuit technologies (silicon CMOS and its extensions such as silicon germanium and silicon on insulator [SOI] and the so-called III-V compound semiconductors including indium phosphide and gallium arsenide), as well as in solid-state sensors such as infrared detectors enabled by the new materials and devices. These new components are being used to enhance the performance of many systems, and even to create systems never before available, of present interest to the U.S. Department of Defense and of likely near-term interest to parts of the commercial electronics industry such as the landline, wireless, and satellite telecommunications industry. These new components require advanced electronic packaging that does not restrict or degrade their performance. Unfortunately largely due to commercial cost pressures, research in and small-lot manufacture of high-performance packaging though still feasible and not lacking for good ideas for possible enhancement, are no longer being actively pursued either by the principal U.S. government agencies (e.g., DARPA, Air Force), by the commercial electronic packaging industry, or by commercial consortia such as the Microelectronics and Computer Technology Corporation (defunct as of June 2000), Semiconductor Research Corporation (SRC), or Sematech Inc. This paper discusses recent examples of high-performance components and integrated circuit technologies and describes how they are being exploited in new or upgraded systems. Advances in packaging technology that will be required to support the new integrated circuits are also described. In conclusion, several possible approaches are reviewed by which the United States can regain momentum in the development of performance-driven packaging technologies.

Advanced multichip module packaging and interconnect issues for GaAs signal processors operating above 1 GHz clock rates

A transceiver includes an antenna having an input for transmitting electrical signals applied thereto. Signal generating means are provided for generating electrical reference signals of a fixed frequency. Transmission means selectively couple the reference signals to the antenna input in response to logic signals. Sensing means digitally indicate the forward voltage waveforms and reverse voltage waveforms on the antenna when the reference signals are applied thereto. A processor is coupled to selectively generate the logic signals and to receive the digital signals indicating the magnitude of the forward voltage and reverse voltage for making signal strength calculations thereon.

High-speed, low-power digital and analog circuits implemented in IBM SiGe BiCMOS technology

Under the auspices of Defense Advanced Research Project Agency Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being explored by Mayo include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation by Mayo to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS technology are presented.

HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY

Under the auspices of Defense Advanced Research Project Agencys Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

Electronic packaging for 10-100 Gb/s OE systems

The minimization of discontinuities in controlled-impedance signal interconnect will be discussed, including novel ideas for extending present packaging fabrication and assembly technology to higher frequency operation.

Corrections to "description and evaluation of the fast-net smart pixel-based optical interconnection prototype"

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.