Alex Guo

InGaAs MOSFETs for CMOS: Recent advances in process technology

InGaAs has recently emerged as the most attractive non-Si n-channel material for future nano-scale CMOS. InGaAs n-channel MOSFETs promise to advance Moores Law by allowing continued scaling through a reduction in footprint and operating voltage without compromising performance. This paper reviews recent advances in some of the key enabling process technology of InGaAs MOSFETs. It also outlines some of the challenges that need to be overcome before this new device family can become a reality.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

We propose and demonstrate a novel test structure to characterize the electrical properties of nano-scale metal-semiconductor contacts. The structure is in essence a two-port transmission line model (TLM) with contacts in the nanometer regime. Unlike the conventional TLM, two types of Kelvin measurements are possible. When performed on devices with different contact spacing, this allows the extraction of the contact resistance, the semiconductor sheet resistance, and the metal sheet resistance. For this, a 2-D distributed resistive network model has been developed. We demonstrate this technique in Mo/n+-InGaAs contacts with contact lengths from 19 to 450 nm where we have measured an average contact resistivity of 0.69±0.3 Ω·μm2. For relatively long contacts , this corresponds to an extremely small contact resistance of 6.6±1.6 Ω·μm.

Positive-bias temperature instability (PBTI) of GaN MOSFETs

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO₂ or a composite SiO₂/Al₂O₃ bilayer were studied. Our research has targeted the evolution of threshold voltage (V_T), subthreshold swing (S) and transconductance (g_m) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V_T shift (ΔV_T) in both gate dielectrics under positive gate stress. In devices with a SiO₂ gate oxide, we have found that ΔV_T is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO₂/Al₂O₃ gate oxide, on the other hand, ΔV_T is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.

Negative-bias temperature instability of GaN MOSFETs

We present a detailed study of the threshold voltage (Vt) instability of GaN n-MOSFETs under negative gate stress. We have investigated Vt shift, subthreshold swing (S) degradation and transconductance (gm) degradation under negative gate voltage stress of different duration at different stress voltages and temperatures. We have found that as stress duration, voltage magnitude and temperature increase, Vt shift (ΔVT) progresses through three regimes. Under low-stress, ΔVT is negative and recoverable, which is a result of electron detrapping from pre-existing oxide traps. Under mid-stress, ΔVT is positive and also recoverable. This appears to be due to temporary electron trapping in the GaN channel under the edges of the gate. For high-stress, there is an additional non-recoverable negative ΔVT, which is consistent with interface state generation.

The effect of neutral beam etching on device isolation in AlGaN/GaN HEMTs

Summary form only given. In this research, we reduced plasma damages on GaN-based high electron mobility transistors (HEMTs) by means of neutral beam (NB) etching. The plasma damages which are induced during dry etching process are one of the causes of decreasing device performances. The NB is almost electrically uncharged and has few UV photons, thus it can reduce plasma damages on the GaN surface. We applied NB etching to the device isolation process, and measured the isolation leakage current under DC and step-stress bias conditions, as well as the breakdown voltages on two-terminal test element arrays. We compared the characteristics with those of samples etched by conventional plasma (PL) etching. The results suggest that the NB etching reduces the leakage current through the deep levels at the etched surface. As a result, the NB samples showed higher breakdown voltages than the PL samples.