Jesús A. del Alamo

Nanometer-Scale Vertical-Sidewall Reactive Ion Etching of InGaAs for 3-D III-V MOSFETs

This letter introduces a novel inductively coupled plasma-reactive ion etching (ICP-RIE) technique based on a BCl3/SiCl4/Ar chemistry for fabricating sub-20 nm diameter InGaAs nanowires with smooth, vertical sidewall and high aspect ratio (>10). To mitigate dry-etch damage, RIE is followed by a digital etch method comprised of multiple cycles of self-limiting low power O2 plasma oxidation and diluted H2SO4 rinse. Using these technologies, we demonstrate vertical InGaAs gateall-around nanowire MOSFETs with 30 nm diameter. Digital etch improves both the subthreshold swing and peak transconductance, indicating enhanced sidewall interfacial quality. The combination of RIE and digital etch techniques proposed here is promising for future 3-D III-V MOSFETs.

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of low-power O₂ plasma oxidation, followed by diluted H₂SO₄ rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ~0.9 nm/cycle. We illustrate the new process by fabricating L_g=60-nm self-aligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO₂ for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/μm(V_ds=0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V_ds=0.05 and 0.5 V, respectively, and on current of 326 μA/μm at I_OFF=100 nA/μm and V_dd=0.5 V.

Novel intrinsic and extrinsic engineering for high-performance high-density self-aligned InGaAs MOSFETs: Precise channel thickness control and sub-40-nm metal contacts

We have fabricated self-aligned tight-pitch InGaAs Quantum-well MOSFETs (QW-MOSFETs) with scaled channel thickness (t_c) and metal contact length (L_c) by a novel fabrication process that features precise dimensional control. Impact of t_c scaling on transport, resistance and short channel effects (SCE) has been studied. A thick channel is favorable for transport, and a mobility of 8800 cm²/V·s is obtained with t_c=11 nm at N_s=2.6×10¹² cm^-2. Also, a record g_m,max of 3.1 mS/μm and R_on of 190 Ω·μm are obtained in MOSFETs with t_c=9 nm and gate length L_g=80 nm. In contrast, a thin channel is beneficial for SCE control. In a device with t_c=4 nm and L_g=80 nm, S is 111 mV/dec at V_ds= 0.5 V. For the first time, working front-end device structures with 40 nm long contacts and gate-to-gate pitch of 150 nm are demonstrated. A new method to study the resistance properties of nanoscale contacts is proposed. We derive a specific contact resistivity between the Mo contact metal and the n⁺ InGaAs cap of ρ=(8±2)×10^-9 Ω·cm². We also infer a metal-to-channel resistance of 70 Ω·μm for 40 nm long contacts.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

We propose and demonstrate a novel test structure to characterize the electrical properties of nano-scale metal-semiconductor contacts. The structure is in essence a two-port transmission line model (TLM) with contacts in the nanometer regime. Unlike the conventional TLM, two types of Kelvin measurements are possible. When performed on devices with different contact spacing, this allows the extraction of the contact resistance, the semiconductor sheet resistance, and the metal sheet resistance. For this, a 2-D distributed resistive network model has been developed. We demonstrate this technique in Mo/n+-InGaAs contacts with contact lengths from 19 to 450 nm where we have measured an average contact resistivity of 0.69±0.3 Ω·μm2. For relatively long contacts , this corresponds to an extremely small contact resistance of 6.6±1.6 Ω·μm.

InGaAs/InAs heterojunction vertical nanowire tunnel fets fabricated by a top-down approach

We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at Vds= 0.3 V is obtained over 2 decades of current. On the same device, Ion= 0.27 μA/μm is extracted at Vdd= 0.3 V with a fixed Ioff= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials.

Off-State Leakage Induced by Band-to-Band Tunneling and Floating-Body Bipolar Effect in InGaAs Quantum-Well MOSFETs

The physics of off-state drain leakage (Ioff) in scaled self-aligned InGaAs quantum-well (QW) MOSFETs is investigated through experiments and simulations. Excess Ioff is observed in InGaAs QW-MOSFETs with very short contact-to-channel spacing. This current bears the marks of band-to-band tunneling (BTBT) that takes place at the drain edge of the channel. However, a pure BTBT current does not explain the observed magnitude of Ioff nor its gate length dependence. For this, we invoke floating-body bipolar amplification of the BTBT current in the QW channel. Device simulations that include BTBT and drift diffusion are consistent with the magnitude of the experimental Ioff and its gate length scaling behavior. The understanding derived here suggests a number of paths to mitigate BTBT-induced off-state current in scaled InGaAs QW-MOSFETs.

Enhancing p-channel InGaSb QW-FETs via Process-Induced Compressive Uniaxial Strain

We study the effect of process-induced uniaxial stress on the performance of biaxially strained InGaSb p-channel quantum-well field-effect transistors (QW-FETs). Uniaxial stress is incorporated using a self-aligned nitride stressor. Compared with unstressed control devices, fabricated stressed devices with a gate length of Lg=0.30 μm showed an increase of more than 40% in the drain current at VGS-VT =-0.5 V and VDS = -2.0\) V, an enhancement of more than 40% in the peak extrinsic transconductance at VDS = -2.0\) V, and a reduction in the source and drain resistance of 25%. These figures suggest an enhancement of the intrinsic transconductance by as much as 60%. The improvement in device characteristics was also found to scale favorably with gate length. The results indicate that process-induced compressive uniaxial strain holds great promise for developing high-performance antimonide-based p-FETs.

Single-Event Transient Response of InGaAs MOSFETs

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms.

Ultra-thin-body self-aligned InGaAs MOSFETs on insulator (III-V-O-I) by a tight-pitch process

We report a self-aligned InGaAs Quantum-Well MOSFET (QW-MOSFET) on III-V-O-I substrate fabricated through a tight-pitch process. The ultra-thin body (UTB) III-V-O-I layer structure was fabricated on Si through a direct bonding technique. The III-V MOSFETs, with a self-aligned gate and metal contacts, were fabricated by a gate-last method. For the first time, we demonstrate adjacent devices with contact metal spacing of 150 nm. The fabrication features CMOS compatibility with a wet-etch free, lift-off free and Au-free process in the front end. Transport and short-channel effects (SCE) are studied as a function of back bias. Excellent SCE control is obtained with DIBL and subthreshold swing benchmarked against state-of-the-art III-V-O-I data. The reported technology provides a new path to integrate III-V front-end devices for future high density circuit applications.

Activation energy of drain-current degradation in GaN HEMTs under high-power DC stress

We have investigated the role of temperature in the degradation of GaN High-Electron-Mobility-Transistors (HEMTs) under high-power DC stress. We have identified two degradation mechanisms that take place in a sequential manner: the gate leakage current increases first, followed by a decrease in the drain current. Building on this observation, we demonstrate a new scheme to extract the activation energy (Ea) of device degradation from step-temperature measurements on a single device. The Ea’s we obtain closely agree with those extracted from conventional accelerated life test experiments on a similar device technology.