Ji-Hyeon Choi

Optical proximity correction considering mask manufacturability and its application to 0.25-μm DRAM for enhanced device performance

A practical optical proximity correction (OPC) method is introduced and applied to 0.25 micrometers DRAM process in order to reduce the gate critical dimension (CD) variations across the exposure field. A variable threshold model is made and evaluated to enhance the model accuracy. This model takes maximum 2X computation time compared with the constant threshold model. The proposed OPC methodology considering both process effects and mask manufacturability simultaneously is discussed in view of the gate line CD variation. The correction segments of a pattern are optimized considering mask manufacturability. Patterns with jog sizes larger than 0.4 micrometers are inspect able with KLA35UV. The OPC results exhibited 60 percent reduction of gate CD variation, 90 percent matching of mean-to-target CD, and 15 percent improvement of circuit performance.

Emergence of assist feature OPC era in sub-130-nm DRAM devices

In this paper, application of assist feature(AF)-OPC for 120nm DRAM device was investigated. For full chip level gate- poly patterning of DRAM device with 120nm design rule, attenuated PSM and OAI(annular type) were used to improve process margin for cell pattern and assist feature(AF) which is a type of OPC for sub-resolution was applied to isolated line in order to reduce iso-dense bias in peripheral area. From simulation and experimental results, the design rule of AF such as AF width, space to main pattern, and main pattern bias was extracted. And manufacturing attenuated PSM with AF, pattern fidelity and defect inspection for mask patterns were considered. Considering the experimental results, we can achieve good iso-dense bias and enlarge the common DOF of 120nm gate pattern with 248nm KrF lithography.

Direction-based topology control algorithm for mobile ad-hop networks

The topology of a mobile ad-hop network can be formed by varying transmission power of each node and this topology can be changed frequently by the mobility of nodes. In this paper, we give a detailed analysis of a direction-based distributed topology control algorithm, termed as HCTC(hill climbing topology control). HCTC is presented for improving connectivity and conserving energy over mobile ad-hop wireless networks. Besides outdoor environment which can use GPS information, applying indoor environment we do not assume that nodes have GPS information available; rather, it depends only on directional information.(Angle of Arrival) HCTC is motivated by the stochastic property of the RWP(random waypoint) mobility model(called border effect); we consider that the border effect can affect a node degree of each node in the deployment region and verify it using an analytical model(fDEG). We also devised HCTCREF algorithm to confirm the topology which formed by proposed algorithm.(HCTC). HCTCREF can verify the direction of reference point which determined by HCTC. Simulation results are presented to demonstrate a set of optimization that further reduce power consumption and prove that they retain robust network connectivity.

Requirements of the inspection for double patterning technology reticles

As the design rule shrinks continuously, a reticle inspection is getting harsh and harsh and is now one of the most critical issues in the mask fabrication process. The reticle inspection process burdens the entire mask process with the inspectability and detectability problems. Not only aggressive assist features but also small and dense main features themselves may cause many false detection alarms or nuisance defects, which makes the inspection TAT (Turn-around Time) longer. Moreover, small and dense patterns inspections always come with the defect detectability issues. Detectability of a defect in small and dense patterns is usually inferior to the printability of it because of the high MEEF (Mask Error Enhancement Factor) resulted by those small and dense patterns. Double Patterning Technology (DPT)[1] can relief the pattern pitch effectively, therefore, DPT reticle pattern can have a larger pitch than normal Single Patterning Technology (SPT) reticle. We investigate the effect of this pitch relaxation of DPT reticle on the inspection process. In this paper, we compare and analyze the difference of pattern inspectability and defect detectability between DPT reticles and SPT reticles when they have same size of patterns on them. In addition to these results, we also investigate the printability of defects in comparison with the detectability and derive the requirement of the inspection for 4x nodes DPT reticles from the results.

Distributed processing (DP) based e-beam lithography simulation with long range correction algorithm in e-beam machine

As the design rule with wafer process is getting smaller down below 50nm node, the specification of CDs on a mask is getting more tightened. Therefore, more tight and accurate E-Beam Lithography simulation is highly required in these days. However, in reality most of E-Beam simulation cases, there is a trade-off relationship between the accuracy and the simulation speed. Moreover, the necessity of full chip based simulation has been increasing in order to estimate more accurate mask CDs based on real process condition. Therefore, without consideration of long range correction algorithm such as fogging effect and loading effect correction in E-beam machine, it would be impossible and meaningless to pursue the full chip based simulation. In this paper, we introduce a breakthrough method to overcome the obstacles of E-Beam simulation. In-house E-beam simulator, ELIS (E-beam LIthography Simulator), has been upgraded to solve these problems. First, DP (Distributed Processing) strategy was applied to improve calculation speed. Secondly, the long range correction algorithm of E-beam machine was also applied to compute intensity of exposure on a full chip based (Mask). Finally, ELIS-DP has been evaluated possibility of expecting or analyzing CDs on full chip base.

Predicting Conversion Time of Circuit Design File by Artificial Neural Networks

GDSII is a data format of the circuit design file for producing semiconductor. GDSII is also used as a transfer format for fabricating photo mask as well. As design rules are getting smaller and RET (Resolution Enhancement Technology) is getting more complicated, the time of converting GDSII to a mask data format has been increased, which influences the period of mask production. Photo mask shops all over the world are widely using computer clusters which are connected through a network, that is, called distributed computing method, to reduce the converting time. Commonly computing resource for conversion is assigned based on the input file size. However, the result of experiments showed that the input file size was improper to predict the computing resource usage. In this paper, we propose the methodology of artificial intelligence with considering the properties of GDSII file to handle circuit design files more efficiently. The conversion time will be optimized by controlling the hardware resource for data conversion as long as the conversion time is predictable through analyzing the design data. Neural networks are used to predict the conversion time for this research. In this paper, the application of neural networks for the time prediction will be discussed and experimental results will be shown with comparing to statistical model based approaches.

Reduction of MDP time through the improvement of verification method

The low-k1 lithography produces large volumes of mask data resulting in more complex optical proximity effect. It puts heavy burden on MDP flow and affects turn around time (TAT). To solve this problem, DP (Distributed Processing) method has been introduced. Even though DP is a very powerful tool to reduce the MDP time, there still might be unexpected pattern drop issue. In order to deal with this issue, the verification step was added in MDP flow. The present verification method is a boolean operation using 2 machine data after converting as a same way. However this verification method has two shortcomings. First, this method is not suitable to detect the same error caused by same software bug. Secondly, it needs double conversion time. A new verification method should be much faster and more accurate than the current verification method. In this paper, the new verification method will be discussed and experimental results using the new verification method will be shown with comparing to the old verification method.

Reduction of MDP complexity through the application of OASIS based data flow

In the IC process, the designed circuit pattern is drawn onto film or glass plate as a photo mask. This original mask is used to transform its transparent pattern onto semiconductor wafers by optical projection. To make photo mask we should convert the design data into a format that the e-beam write tool can understand. This MDP (Mask Data Preparation) process is getting more and more complicated to support many kinds of e-beam data format which is required not only for each electron beam writers but die to database inspection tools. It gives us a burden to treat various MDP flow and this may impact on turn around time (TAT). Therefore, it becomes more necessary to make MDP flow simpler by unifying the various mask data formats. Moreover it is required to suppress huge data volume due to design rule shrink and aggressive OPC. To address these issues, the Open Artwork System Interchange Standard (OASISTM) has been approved by the EDA industry and is officially announced by SEMI Data Path Task Force. OASIS data format allows the reduction in file size compared to GDSII while the processing time such as MRC and MDP is not influenced. Also OASIS is effective in reducing complexity of mask data preparation flow. In this paper, the implementation of OASIS format within mask data preparation flow will be discussed and experimental results of OASIS-based data flow will be shown with comparing to traditional GDSII/MEBES-based data flow.

Analysis of dose modulation method for fogging effect correction at 50-KeV e-beam system

In this paper, the influence of dose modulation on CD trend by using electron beam exposure model has been investigated and simulated. To predict CD trend, we developed an analysis program, which shows the exposed energy profile and the corrected CD distribution in mask. First, it calculates the factor of fogging effect correction (Df) from pattern density distribution with the assumption that fogging effect depends on only pattern density. And then it calculates the modified dose for correcting both proximity and fogging effect. From dose distribution, the corrected CD is calculated analytically by using e-beam lithography model: see Figure 1. It can give a glance how the dose modulation method has an influence on the CD uniformity. Moreover, the result of global error correction such as side, radial error at the mask writing stage has been analyzed in this study.

Simulation of mask CD variation for different local densities with in-house developed e-beam lithography simulator

E-beam lithography simulation is one of the effective tools for understanding the complex e-beam lithography process. In-house E-beam Lithography Simulator, ELIS, has been developed in order to analyze the mask CD errors. ELIS adopts the Monte Carlo method to accurately describe the electron scattering and energy deposition on the resist, and fits this result with more than two Gaussians to convolute with pattern shape efficiently and rapidly. This simulator provides the function of the proximity effect correction (PEC) and fogging effect correction. ELIS, moreover, can simulate the post exposure bake step (PEB), therefore, latent image and resist profile is given for chemically amplified resists (CAR). From the exposure simulation with ELIS, the amoung of CD variation regarding different density patterns in various conditions can be predicted. The simulation results are matched with experimented values within 5% error. Even though PEC corrects perfectly, the non-zero mean-to-target (MTT) induces the CD error. The CD errors with dose modulation and GHOST along with the MTT variation have been studied with ELIS. Also, we show these errors increasing after applying fogging effect correction.