Byeong-soo Kim

Emergence of assist feature OPC era in sub-130-nm DRAM devices

In this paper, application of assist feature(AF)-OPC for 120nm DRAM device was investigated. For full chip level gate- poly patterning of DRAM device with 120nm design rule, attenuated PSM and OAI(annular type) were used to improve process margin for cell pattern and assist feature(AF) which is a type of OPC for sub-resolution was applied to isolated line in order to reduce iso-dense bias in peripheral area. From simulation and experimental results, the design rule of AF such as AF width, space to main pattern, and main pattern bias was extracted. And manufacturing attenuated PSM with AF, pattern fidelity and defect inspection for mask patterns were considered. Considering the experimental results, we can achieve good iso-dense bias and enlarge the common DOF of 120nm gate pattern with 248nm KrF lithography.

Era of double exposure in 70 nm node DRAM cell

In this paper, two different methods of double exposure are proposed to improve the resolution in low k1 lithography. One is using an additional mask to complement the lack of image contrast. The other is to fix the mask and only use combinations of illumination systems to increase image contrast. By applying image assisting double exposure to asymmetry dense contact under k1=0.33, the process window can be doubled in comparison to the single exposure method. By an appropriate design of two masks, we could also minimize the image distortion from overlay shift by mixture of masks. Effective first order efficiency is defined as a new term in double exposure with complementary illumination. The larger the value is, the better the image contrast becomes. Through an experiment and simulation in k1=0.30, in double exposure with two illuminations and the same mask, that wider process window was obtained than in single exposure with optimized illumination system, and also 0.10um of DOF (Depth of Focus) was obtained under k1=0.28.

ArF issues of 90-nm-node DRAM device integration

Recently, the design rule shrinkage of DRAM devices has been accelerated. According to International Technology Roadmap for Semiconductor (ITRS) 2001, 90 nm node will start in 2004. For this achievement, lithography has been standing especially in the forefront and leading the ultra fine patterning technologies in the manufacturing of semiconductor devices. We are now in the moment of transition from the stronghold of KrF to the prospective of ArF. In this paper, we applied ArF process to the real DRAM devices of 90nm node. We proved good pattern fidelity and device performance. The ArF process, however, has still some weak points - resist shrinkage and LER (Line Edge Roughness). Resist shrinkage is very crucial problem for measuring CD. To overcome it, we applied ASC (Anti-Shrinkage Coating) process to ArF resist and improved the CD measurement. LER also becomes an issue, as the design rule is shrink. It is found that they are very dependent on resist type. However, it could be cured effectively by VUV treatment. Finally we will mention the current status of low k1 factor and the future lithographic strategy of which technologies will be most feasible based on current situation.

One step forward to maturity of AF (assistant feature)-OPC in 100-nm level DRAM application

For 100nm-level patterning using optical lithography, high NA system and various RETs such as PSM, off-axis illumination and OPC are obviously required. In particular, assistant feature (AF)-OPC is indispensable to overcome narrow depth of focus (DOF) caused by iso-dense bias and to compensate for linearity difference under the given OAI condition. Previously we reported the application of AF-OPC in DRAM process with 120nm design rule. The extraction of OPC rule and the feasibility of AF-OPC were successfully confirmed by experimental method in real process. In this paper, more comprehensive and aggressive AF-OPC rule is investigated. The old rule is modified in order to obtain larger common DOF. TO avoid dead zone that means discontinuity between dense line and semi-dense line, we apply a comprehensive rule such as insertion of AF between the neighboring main patterns as many as possible. As a result, the discontinuity of OPC application, which is used with or without AF in the boundary region, is effectively minimized. Also, polygon-shaped AF is used to improve DOF of special main pattern. And then, the mask specification and the behavior of isolated line pattern are predicted in case of very high NA KrF and ArF lithography by simulation result. Considering 100nm design rule, the decrease of common DOF is expected to be severer than now. Finally, the optimum AF-OPC rules such as AF size, space and shape are available and shown in case of very high NA KrF and ArF lithography.

Lithography process design for 4-Gb DRAM of 0.31 K1 with KrF

We studied lithography process of 0.31 k1 for DRAM device with KrF light source. DRAM device with 100 nm half-pitch design rule, which can facilitate 4 Giga-bit in a chip, can be patterned with the aid of super resolution enhancement techniques (SRET) and high NA (equals0.7) KrF scanner. The SRET includes the use of strong off-axis illumination (OAI) and attenuated phase shift mask (8% transmittance). In the case of using the SRET, those of very large iso-dense (I-D) bias from the optical proximity effect (OPE), narrow depth of focus (DOF) of (semi-) isolated features and existence of dead-zone in the peripheral circuit and so forth, are emerging as critical issues to be solved except the very fundamental lens aberration. These problems can only be solved when aggressive optical proximity correction (OPC) techniques such as selective bias and assistant feature to (semi-) isolated features are used for every critical layer of the device, where the OPC rules were generated from simulations and empirical experiments. Besides OPC techniques, close and cooperative approach of lithographers and designers is also necessary for the process oriented layout design especially to avoid the dead-zone that SRET generates. We have tried to customize the lithography process design for 0.31 k1 and finally obtained the common process latitude to make the full 4 Giga-bit DRAM device lithography feasible on this basis.

Mask considerations for manufacturing assist features

Assist features are recently employed in high density devices. But the application seems to be burdening to mask manufacturers. In this paper, considerations for making masks bearing assist features are discussed. A mask grid size, minimum resolution, CD linearity, pattern fidelity, and mask inspectability are among those considerations. For a 0.13 micrometer node, the grid size <EQ 5 nm (4X) is recommended according to our simulation. A high acceleration voltage (50 keV) e-beam writer is found to be a good tool for 0.26 micrometer (4X) assist features necessary for 0.13 micrometer node. A currently available inspection machine should give a good potential to detect defects on a 0.18 micrometer (4X) assist feature bearing mask.

Application of phase-edge PSM for narrow logic gate

Phase-Shifting Mask (PSM) technology is one of the most practical resolution enhancement technologies for fine patterning using the DUV wavelength (248 nm) without employing a new exposure system. In this paper, we applied phase-edge PSM to 0.13 micrometer logic device and investigated the process latitude depending on the mask issues such as phase error, defect, bias, etc. In manufacturing phase-edge mask, the bias method was applied to layout generation in order to correct pattern displacement caused by space CD difference between shifter and non-shifter region. Also the effects of phase error and phase defect were examined and confirmed by simulation and experimental method. Moreover, in order to achieve more accurate CD control, optimization of trim mask design was performed for reducing linewidth variations during double exposure. With design rules extracted from simulation and experiment, the layout generation of full chip level gate layer was done by EDA software. By double exposure method using KrF scanner with 0.6 NA system, 0.13 micrometer logic gate patterns were printed successfully with good process margin and sub-0.10 micrometer patterns with good profile were resolved, which shows the possibility of further optical extension using phase-edge PSM.