Jian-Yu Hsieh

21.6 A smart CMOS assay SoC for rapid blood screening test of risk prediction

Rapid blood test is essential to disease control, risk assessment and point-of-care testing. Conventional enzyme-linked immunosorbent assay (ELISA) requires several hours or even days to get meaningful results. However, to some fierce contagious diseases, such as Ebola and SARS, the contagion can spread so fast that an instant and massive screening test is needed. A CMOS assay system-on-chip (SoC) offering a fast and cheap disease screening tool can be very helpful in the place where the medical resources are limited and the test is too costly to afford. Unlike the previously proposed CMOS biomolecular detection based on direct detection [1], a sandwiched assay detection protocol is adopted in this work, which possesses high sensitivity, high specificity and is free from pre-purified antigen process. As shown in Figure 1, a human blood sample containing the target biomolecules is applied on the proposed SoC. The test procedure includes blood filtration, biomolecular conjugation, electrolytic pumping, magnetic flushing and detection, automatically controlled by a micro-controller unit (MCU). The biomolecular signal is converted to the electrical signal by a CMOS-based Hall sensor array, as shown in the SEM image of Fig. 21.6.1, where the surface is coated with biomolecular probe. With the integration of the four LEDs and a battery, the detection steps can be indicated, providing an easy self-test point-of-care application.

A Smart CMOS Assay SoC for Rapid Blood Screening Test of Risk Prediction

A micro-controller unit (MCU) assisted immunoassay lab-on-a-chip is realized in 0.35 μm CMOS technology. The MCU automatically controls the detection procedure including blood filtration through a nonporous aluminum oxide membrane, bimolecular conjugation with antibodies attached to magnetic beads, electrolytic pumping, magnetic flushing and threshold detection based on Hall sensor array readout analysis. To verify the function of this chip, in-vitro Tumor necrosis factor- α (TNF- α) and N-terminal pro-brain natriuretic peptide (NT-proBNP) tests are performed by this 9 mm 2-sized single chip. The cost, efficiency and portability are considerably improved compared to the prior art.

A Remotely-Controlled Locomotive IC Driven by Electrolytic Bubbles and Wireless Powering

As implantable medical CMOS devices become a reality [1], motion control of such implantable devices has become the next challenge in the advanced integrated micro-system domain. With integrated sensors and a controllable propulsion mechanism, a micro-system will be able to perform tumor scan, drug delivery, neuron stimulation, bio-test, etc, in a revolutionary way and with minimum injury. Such devices are especially suitable for human hollow organs, such as urinary bladder and stomach. Motivated by the art reported in ISSCC 2012 [2], we demonstrate a remotely-controlled locomotive CMOS IC which is realized in TSMC 0.35μm technology. As illustrated in Fig. 18.7.1, a bare CMOS chip flipped on a liquid surface can be moved to the desired position without any wire connections. Instead of Lorentz forces [2], this chip utilizes the gas pressure resulting from electrolytic bubbles as the propulsive force. By appointing voltages to the on-chip electrolysis electrodes, one can decide the electrolysis location and thereby control the bubbles emissions as well as the direction of motion. With power management circuits, wireless receiver and micro-control unit (MCU), the received signal can be exploited as the movement control as well as wireless power. Experiments show a moving speed of 0.3mm/s of this chip. The total size is 21.2mm2 and the power consumption of the integrated circuits and the electrolysis electrodes are 125.4μW and 82μW, respectively.

A 1.5-mW, 2.4 GHz Quasi-Circulator With High Transmitter-to-Receiver Isolation in CMOS Technology

A 2.4 GHz active quasi-circulator is implemented in TSMC 0.18 μ m CMOS technology. We propose a new architecture using current-reuse and adjustable signal cancellation to achieve a low-power, high-isolation and small-size circulator. The measured isolation from transmitter to receiver, |S31|, can be as high as 68 dB, which to our knowledge is the highest value ever reported in integrated circulators. Other isolations, such as receiver-to-transmitter, receiver-to-antenna, and antenna-to-transmitter isolations, are all better than 28 dB. The total power consumption is only 1.5 mW with a chip size of 820 μm × 750 μm including bypass capacitors and pads.

Gold Plated Carbon Nanotube Bundle Antenna for Millimeter-Wave Applications

A gold plated carbon nanotube (CNT) bundle antenna, which is integrated with a voltage control oscillator (VCO) is reported. Gold plating reduces ohmic loss and improves radiation efficiency of the CNT antenna. Reflection measurements of the antenna show a return loss of 12 dB at 67 GHz and -6 dB impedance bandwidth at 53-87.5 GHz, 140-168 GHz, and 207-220 GHz, respectively. The VCO implemented in 65-nm CMOS technology is designed to be integrated with the antenna for the measurement of antenna gain. The measurement result of the antenna gain is -9.7 dBi at 50.7 GHz. These experimental results demonstrate that the proposed antenna is very promising for millimeter-wave applications.

A 2–6GHz broadband CMOS low-noise amplifier with current reuse topology utilizing a noise-shaping technique

A 2-6GHz broadband low-noise amplifier (LNA) with current reuse and noise-shaping technique is proposed for wideband matching, high power gain and flat noise figure (NF) response. The proposed UWB LNA is implemented in TSMC 0.18um CMOS technology. Measured results show that power gain is greater than 15dB and input return loss is larger than 10dB from 2 to 6GHz. The input third-order intercept point (IIP3) is −4dBm. Besides, a good noise figure of 3–3.7dB is obtained over the band of interest with a power dissipation of 15mW under a 1.8V power supply.

A low-power millimeter wave VCO by using frequency doubling technique

A compact low-power VCO in 0.18 μm CMOS technology is presented for V-band applications. Unlike conventional push-push VCOs using huge passive transmission-line-based frequency doublers to rise their output oscillation frequencies, the proposed VCO adopts a more compact transistor-based frequency doubler to reduce chip layout area. Under 1-V supply operation, experimental results show that the output power of VCO ranges from -13.5 dBm to -6.5 dBm over the V band of interest with low power dissipation from 6.3 mW to 16.1 mW excluding the output buffer. The measured phase noise is -93.12 dBc/Hz at 10MHz offset from 55 GHz carrier. This VCO only occupies a small chip layout area of 0.1 mm2 excluding pads and bypass capacitors.

A 90-nm CMOS V-Band Low-Power Image-Reject Receiver Front-End With High-Speed Auto-Wake-Up and Gain Controls

A low-power auto-wake-up image-reject receiver front-end in 90-nm CMOS technology is presented for V-band applications. The proposed front-end generally operates in the sleep mode and consumes 19 mW. When an RF signal greater than -50 dBm is received, the front-end wakes up automatically and enters into the active mode consuming only 46-mW power. Adjustable linearity (IP1dB) of the front-end is provided by changing two gain modes (high- and low-gain modes). When input RF power is higher than -30 dBm, IP1dB will be improved (from high-gain mode to low-gain mode). Experiments show IP1dB of -25.2 and -22.5 dBm in high- and low-gain modes, respectively. An image-reject ratio greater than 32 dB is measured when using the proposed image-reject mixer topology. All passive phase-shift couplers for realizing the image-rejection are composed of standard CMOS lumped elements, thereby considerably reducing the chip size (0.82 mm 2).

A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18

A 0.45-V low-power 0.18 μm CMOS OOK/FSK RF receiver for implantable medical applications is proposed. The receiver utilizes a wake-up mechanism to adjust its power consumption automatically by reading the amplitude of the input wireless OOK/FSK modulated RF signal directly. No additional wireless wake-up commands are required. Such a normally-off and instanton scheme reduces the power consumption of this receiver significantly. The power consumption is 129 μW in sleep mode and 352 μW in wake-up mode. Other techniques, such as third-orderharmonic cancellation, subharmonic mixing, and forward body biasing are also adopted for better linearity, higher LO-to-RF isolation, and lower VDD, respectively. The measurement results show that the proposed receiver consumes only 2.6 nJ/bit (OOK) and 1 nJ/bit (FSK) to achieve the sensitivities of -55 dBm (OOK) and -53.5 dBm (FSK) in BER <; 10-3 constraint. The proposed receiver is designed for low-power and short-distance MICS band applications.