Kuan-Ting Lin

A 2.1 to 6 GHz Tunable-band LNA With Adaptive Frequency Responses by Transistor Size Scaling

A 2.1 to 6 GHz tunable-band LNA by using transistor-size scaling technique is realized in 90 nm CMOS technology, which adopts a scalable-size transistor mimicked by the parallel-connected transistors with binary weighted device sizes. In the 16 programmable bands located in the frequencies of interest, the S21 varies in the range from 15.1 to 16.9 dB, and the NF is from 2.16 to 2.81 dB. This tunable -band LNA occupies only 0.23 mm2, which is readily compact compared with the prior arts of passive components switchable LNAs.

Gold Plated Carbon Nanotube Bundle Antenna for Millimeter-Wave Applications

A gold plated carbon nanotube (CNT) bundle antenna, which is integrated with a voltage control oscillator (VCO) is reported. Gold plating reduces ohmic loss and improves radiation efficiency of the CNT antenna. Reflection measurements of the antenna show a return loss of 12 dB at 67 GHz and -6 dB impedance bandwidth at 53-87.5 GHz, 140-168 GHz, and 207-220 GHz, respectively. The VCO implemented in 65-nm CMOS technology is designed to be integrated with the antenna for the measurement of antenna gain. The measurement result of the antenna gain is -9.7 dBi at 50.7 GHz. These experimental results demonstrate that the proposed antenna is very promising for millimeter-wave applications.

A 0.8–6 GHz Wideband Receiver Front-End for Software-Defined Radio

A wideband (0.8–6 GHz) receiver front-end (RFE) utilizing a shunt resistive feedback low-noise amplifier (LNA) and a micromixer is realized in 90 nm CMOS technology for software-defined radio (SDR) applications. With the shunt resistive feedback and series inductive peaking, the proposed LNA is able to achieve a wideband frequency response in input matching, power gain and noise figure (NF). A micromixer down converts the radio signal and performs single-to-differential transition. Measurements show the conversion gain higher than 17 dB and input matching (S11) better than −7.3 dB from 0.8 to 6 GHz. The IIP3 ranges from −7 to −10 dBm, and the NF from 4.5 to 5.9 dB. This wideband receiver occupies 0.48 mm2 and consumes 13 mW.

A 2–6GHz broadband CMOS low-noise amplifier with current reuse topology utilizing a noise-shaping technique

A 2-6GHz broadband low-noise amplifier (LNA) with current reuse and noise-shaping technique is proposed for wideband matching, high power gain and flat noise figure (NF) response. The proposed UWB LNA is implemented in TSMC 0.18um CMOS technology. Measured results show that power gain is greater than 15dB and input return loss is larger than 10dB from 2 to 6GHz. The input third-order intercept point (IIP3) is −4dBm. Besides, a good noise figure of 3–3.7dB is obtained over the band of interest with a power dissipation of 15mW under a 1.8V power supply.

A low-power millimeter wave VCO by using frequency doubling technique

A compact low-power VCO in 0.18 μm CMOS technology is presented for V-band applications. Unlike conventional push-push VCOs using huge passive transmission-line-based frequency doublers to rise their output oscillation frequencies, the proposed VCO adopts a more compact transistor-based frequency doubler to reduce chip layout area. Under 1-V supply operation, experimental results show that the output power of VCO ranges from -13.5 dBm to -6.5 dBm over the V band of interest with low power dissipation from 6.3 mW to 16.1 mW excluding the output buffer. The measured phase noise is -93.12 dBc/Hz at 10MHz offset from 55 GHz carrier. This VCO only occupies a small chip layout area of 0.1 mm2 excluding pads and bypass capacitors.

A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling

In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, −28/−27dBm of P1dB, −16/−16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.