Jianfeng Gao

Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells

Developing high performance self-selective cell (SSC) is one of the most critical issues of the integration of 3D vertical RRAM (V-RRAM). In this work, a four-layer V-RRAM array, with high performance HfO2/mixed ionic and electronic conductor (MIEC) bilayer SSC, was demonstrated for the first time. Several salient features were achieved, including ultra-low half-select leakage (<;0.1 pA), very high nonlinearity (>103), low operation current (nA level), self-compliance, high endurance (>107), and robust read/write disturbance immunity.

CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask

We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO2 nanostructures using a single amorphous silicon (α-Si) mask layer. The α-Si mask pattern is precisely transferred into the underlying SiO2 substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used as an etch mask to fabricate SiO2 nanostructures including nanoline, nanotrench, and nanohole arrays. It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls. This behavior may be attributed to the presence of high concentration of dangling bonds in α-Si mask surface. By controlling the process condition, it is possible to achieve a desired vertical etched profile with a controlled size. Our results demonstrate that SiO2 pattern as small as sub-20xa0nm may be achievable. The obtained SiO2 pattern can be further used as a nanotemplate to produce periodic or more complex silicon nanostructures. Moreover, this novel top-down approach is a potentially universal method that is fully compatible with the currently existing Si-based CMOS technologies. It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low VT. Compared with halo doping with the same VT,sat at VDD = 0.8 V, despite no ION enhancement, the SPW reduces DIBL by 45% and enhances IEFF by 18%. Compared with halo doping with the same IOFF = 100 nA/μm at VDD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances ION by 5%, and improves IEFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT)

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

A novel nanofabrication technique which can produce highly controlled silicon-based nanostructures in wafer scale has been proposed using a simple amorphous silicon (α-Si) material as an etch mask. SiO2 nanostructures directly fabricated can serve as nanotemplates to transfer into the underlying substrates such as silicon, germanium, transistor gate, or other dielectric materials to form electrically functional nanostructures and devices. In this paper, two typical silicon-based nanostructures such as nanoline and nanofin have been successfully fabricated by this technique, demonstrating excellent etch performance. In addition, silicon nanostructures fabricated above can be further trimmed to less than 10xa0nm by combing with assisted post-treatment methods. The novel nanofabrication technique will be expected a new emerging technology with low process complexity and good compatibility with existing silicon integrated circuit and is an important step towards the easy fabrication of a wide variety of nanoelectronics, biosensors, and optoelectronic devices.

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the devices scaling.

Study on the Effect of Plasma Treatment on Flat-band-voltage andEquivalent Oxide Thickness using Metal-organic Chemical VaporDeposition TiN Film as p-MOSFETS Metal Gate Electrode

This work aimed to study on the effects of plasma treatment on flat band voltage (Vfb) and equivalent oxide thickness (EOT) using Metal-organic Chemical Vapor Deposition (MOCVD) TiN film as p-MOSFETs metal gate electrode. Theplasma treatment conditions effect on the resistance and composition properties of MOCVD TiN, consequently, they can modulate work function and control threshold voltage. The effects of “plasma treatment” were imposed to favor the formation of Ti-N bonds, thus decreasing the rate Ti-C bond and favoring a crystallized stoichiometric TiN phase to increase PMOS Vfb shift. Meanwhile, plasma treatments accelerate interfacial oxide formation and increase EOT. On the other hand, EOT increases with the increase of plasma treatment time and power in this work, but Vfb does not always increase and reach a max value.

Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical vapor deposition titanium/chemical vapor deposition titanium nitride (ALD TiN/PVD Ti/CVD TiN) MG in devices of short channels is larger than in devices of long channels. This mainly results from different ALD TiN crystal orientations for devices with different gate lengths, that is, TiN(100) for devices with short gate length, whereas TiN(111) for devices with long gate length. The WF of ALD TiN(100) is larger than TiN(111). Meanwhile, because of the property of PVD sputtering, the Ti layer is thinner in devices of short channels than in devices of long channels. Our results on MOSCAP show that the flat-band voltage (Vfb) for TiN MG with a Ti layer is reduced by 0.2 V. Taking all the aforementioned into account, Vth roll-up is suppressed as the gate length shrinks, leading to the mitigation of RSCE.

A straightforward and CMOS-compatible nanofabrication technique of periodic SiO2 nanohole arrays.

In this work, we have demonstrated a straightforward and CMOS-compatible nanofabrication technique that can produce well-ordered periodic SiO2 nanohole arrays in wafer-scale using a single amorphous silicon (α-Si) layer. It is the first time that α-Si material has been used as an etch mask to fabricate SiO2 nanostructures. Our results have shown that the diameter and shape of SiO2 nanohole arrays, with vertical and smooth sidewalls, can be precisely controlled by an optimized two-step etch process. The diameter and pitch of nanoholes as small as 45 nm and 140 nm, respectively, have been successfully achieved. Moreover, the technique is independent of any specific lithographic approaches and, therefore, is capable of fabricating SiO2 nanohole arrays with smaller diameters and higher densities. Furthermore, since our approach is completely metal-free, it can be incorporated and integrated very easily into the standard semiconductor industry. It has a potential for wide applications in micro-nanofabrication, and represents a big step towards mass production.

Cost-effective amorphous silicon hard mask patterning sub-45nm contact trench

A cost-effective process fabricating nanoscale SiO2 contact trench below 45nm was developed using amorphous silicon hard mask in a CCP etcher. When using both photo resist (PR) and α-Si hard mask to etch SiO2 layer, a typical problem of sidewall bowing was observed due to polymer accumulation on both sides of mask and effect of deviated ions from normal direction. It is more favorable using simple α-Si to etch SiO2 by an additional PR strip step. Finally, a slightly tapered contact trench has been achieved without visible sidewall bowing, which will be useful for metal filling in the trench.