Lingkuan Meng

Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate

In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate devices with rectangular or trapezoidal fins. It is due to formation of quasi-surrounding gate electrodes on scalloping fins by a special Si etch process. The entire integration flow of the S-FinFETs is fully compatible with the mainstream all-last HKMG FinFET process, except for a modified fin etch process. The drain-induced barrier lowering and subthreshold swing of the fabricated p-type S-FinFETs with a 14-nm physical gate length are 62 mV/V and 75 mV/dec, respectively, which are much better than those of normal FinFETs with a similar process. With an improved short-channel-effect immunity in the channels due to structure modification, the novel structure provides one of possibilities to extend the FinFET scalability to sub-10-nm nodes with little additional process cost.

Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure

In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the poly-silicon gate etch based on the composite SiO 2 /Si 3 N 4 /SiO 2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO 2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon ( α -Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low VT. Compared with halo doping with the same VT,sat at VDD = 0.8 V, despite no ION enhancement, the SPW reduces DIBL by 45% and enhances IEFF by 18%. Compared with halo doping with the same IOFF = 100 nA/μm at VDD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances ION by 5%, and improves IEFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT)

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the devices scaling.

Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical vapor deposition titanium/chemical vapor deposition titanium nitride (ALD TiN/PVD Ti/CVD TiN) MG in devices of short channels is larger than in devices of long channels. This mainly results from different ALD TiN crystal orientations for devices with different gate lengths, that is, TiN(100) for devices with short gate length, whereas TiN(111) for devices with long gate length. The WF of ALD TiN(100) is larger than TiN(111). Meanwhile, because of the property of PVD sputtering, the Ti layer is thinner in devices of short channels than in devices of long channels. Our results on MOSCAP show that the flat-band voltage (Vfb) for TiN MG with a Ti layer is reduced by 0.2 V. Taking all the aforementioned into account, Vth roll-up is suppressed as the gate length shrinks, leading to the mitigation of RSCE.

High-quality HfSiON gate dielectric and its application in a gate-last NMOSFET fabrication

HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET. In the process, poly-silicon was deposited on HfSiON gate dielectric as dummy gate and replaced by TaN metal gate after source/drain formation. Because of the metal gate formation after the ion-implant doping activation at high temperature, HfSiON/TaN NMOSFET with good driving ability and excellent sub-threshold characteristics was fabricated.

Silicon Photonics Process Development Based on A 200-mm CMOS Platform

In this paper, the process difference between Si photonics and Si CMOS is discussed. Firstly, the substrate of Si photonics and the issues about electronic-photonic integration are commented . Lithography, etching and hydrogen annealing are then discussed in detail. Line edge roughness is thought to be the original source of scattering loss of waveguide. Hydrogen annealing is effective to reduce the sidewall roughness but has the risky of changing the profile of waveguide. Ion implantation and metallization for active photonics components can be easily transferred from the CMOS process recipes. Ge photodetector fabrication is challenging though it shares the same epitaxy equipment with the CMOS platform. Finally, a whole Si photonics process flow including passive and active components based on our 200 mm CMOS platform is presented.

A straightforward and CMOS-compatible nanofabrication technique of periodic SiO2 nanohole arrays.

In this work, we have demonstrated a straightforward and CMOS-compatible nanofabrication technique that can produce well-ordered periodic SiO2 nanohole arrays in wafer-scale using a single amorphous silicon (α-Si) layer. It is the first time that α-Si material has been used as an etch mask to fabricate SiO2 nanostructures. Our results have shown that the diameter and shape of SiO2 nanohole arrays, with vertical and smooth sidewalls, can be precisely controlled by an optimized two-step etch process. The diameter and pitch of nanoholes as small as 45 nm and 140 nm, respectively, have been successfully achieved. Moreover, the technique is independent of any specific lithographic approaches and, therefore, is capable of fabricating SiO2 nanohole arrays with smaller diameters and higher densities. Furthermore, since our approach is completely metal-free, it can be incorporated and integrated very easily into the standard semiconductor industry. It has a potential for wide applications in micro-nanofabrication, and represents a big step towards mass production.

Cost-effective amorphous silicon hard mask patterning sub-45nm contact trench

A cost-effective process fabricating nanoscale SiO2 contact trench below 45nm was developed using amorphous silicon hard mask in a CCP etcher. When using both photo resist (PR) and α-Si hard mask to etch SiO2 layer, a typical problem of sidewall bowing was observed due to polymer accumulation on both sides of mask and effect of deviated ions from normal direction. It is more favorable using simple α-Si to etch SiO2 by an additional PR strip step. Finally, a slightly tapered contact trench has been achieved without visible sidewall bowing, which will be useful for metal filling in the trench.