Jianhui Bu

A compact model for the STI y-stress effect on deep submicron PDSOI MOSFETs

The shallow trench isolation (STI) y-stress effect on deep submicron PDSOI MOSFETs was studied. Instance parameters SAy, SBy and model parameters a1, a2, b1, b2 were proposed to build a compact model for this effect. This model can be easily implemented in the SOI MOSFET compact model like BSIMSOI model. By using this model, we can simulate the STI y-stress effect well, especially for the changes of Idsat and Vtlin.

Effect of cryogenic temperature characteristics on 0.18-μm silicon-on-insulator devices*

The experimental results of the cryogenic temperature characteristics on 0.18-μm silicon-on-insulator (SOI) metal-oxide-silicon (MOS) field-effect-transistors (FETs) were presented in detail. The current and capacitance characteristics for different operating conditions ranging from 300 K to 10 K were discussed. SOI MOSFETs at cryogenic temperature exhibit improved performance, as expected. Nevertheless, operation at cryogenic temperature also demonstrates abnormal behaviors, such as the impurity freeze-out and series resistance effects. In this paper, the critical parameters of the devices were extracted with a specific method from 300 K to 10 K. Accordingly, some temperature-dependent-parameter models were created to improve fitting precision at cryogenic temperature.

The STI stress effect on deep submicron PDSOI MOSFETs

The STI stress effect is investigated based on the 0.13 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). It shows that the threshold voltage and mobility are all affected by the STI stress. The absolute value of the threshold voltage of NMOS and PMOS increased by about 10%, the saturation current of NMOS decreases by about 20%, while the saturation current of PMOS increases by about 20%. It is also found that the lower temperature enhances the STI stress and then influences the device performance further. Then a macro model for this effect is proposed and is well verified.

A simulation model for the PN junction based on SOI

The shallow junction is used in the PDSOI technology. Unfortunately, the standard diode model maybe not suit to this PN junction. A simulation model is proposed based on the PDSOI process. The additional influence of the voltage bias of the junction to the capacitance is considered in this model and then the model is well verified by the measured data.

A simulation model for PDSOI MOSFETs

The shallow source and drain is used in the PDSOI technology. Unfortunately, most of the standard commercial SOI MOSFET model is for the device with deep source and drain, the necessity of the new models for this device arises. A simulation model is proposed based on the 0.13μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and then the model is well verified by the ring-oscillator.

A bias dependent body resistance model for deep submicron PDSOI technology

We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35µm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.