Jianwen Luo

A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 μm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis.

Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications

This brief presents an energy- and area-efficient discrete wavelet packet transform (DWPT) processor design for power-constrained and cost-sensitive healthcare-monitoring applications. This DWPT processor employs recursive memory-shared architecture to achieve low hardware complexity while performing required arbitrary-basis DWPT decomposition. By exploiting inherent characteristics of different physiological signals through an entropy statistic engine, the DWPT processor core can be reconfigured to compute multilevel wavelet decomposition with effective time and frequency resolution. Various design techniques from algorithm to circuit levels, including reconfigurable computing, lifting scheme, dual-port pipeline processing, near-threshold operation, and clock gating, are applied to achieve energy efficiency. With a 0.18-μm CMOS technology at 0.5 V and 1 MHz, the DWPT core only consumes 26 μW for performing three-level 256-point DWPT decomposition with entropy statistic calculation. When integrated in an ARM Cortex-M0-based biomedical system-on-a-chip test platform, the DWPT processor achieves processing acceleration by three orders of magnitude and reduces energy consumption by four orders of magnitude compared with CPU-only implementations.

Ultra-low-energy near-threshold biomedical signal processor for versatile wireless health monitoring

In this paper, an ultra-low-energy biomedical signal processor (BSP) is proposed for wireless multi-channel physiological signal monitoring. This BSP integrates a RISC core and application-specific hardware accelerators (ASHAs) to achieve ultra low power consumption while meeting required performance. Various low power design techniques from system to circuit levels are applied, including event-driven signal processing, dynamic clock management, near-threshold operation, glitch-free clock generation, fine-grain clock gating, and ultra-low-voltage level shifting. The BSP can operate with supply from 1.8V down to 0.5V. With integrated ECG ASHAs based on the discrete wavelet transform, its overall energy consumption is 20.4pJ/cycle at 0.5V and 10MHz when performing a real-time wireless ECG monitoring.

A 457-nW cognitive multi-functional ECG processor

In this paper, a multi-functional ECG signal processor for wearable and implantable real-time monitoring is presented. To enable extremely long-term ambulatory monitoring, several power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An on-chip low-complexity cardiac signal analysis module is proposed to realize comprehensive analysis functions. Near-threshold circuit technique is applied to the overall system. Implemented in 0.18 μm CMOS, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V supply for real-time ambulatory monitoring. Compared with existing designs, the presented ECG processor achieves the lowest power consumption.

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing

An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively.

A tactile sensor ASIC for a sensorized guidewire in minimally invasive surgical operations

In this paper, a tactile sensor ASIC for a sensorized guidewire in minimally invasive surgical operations is presented. This ASIC interfaces with Silicon Nanowire (SiNW) sensors, which capture the force exerted at the tip of the guidewire and present it as a resistance value. The resistance is then converted to current pulses in the ASIC. These pulses are transmitted and displayed on an external monitoring module through a 3-wire interconnect, which is also used to carry the control signals and the power supplies for the ASIC. There are three major challenges: limited area due to the integration at the tip of the guidewire together with the sensors, restricted number of interconnecting wires through the guidewire, and huge resistance variations in the SiNW sensors. These challenges are addressed through an incremental double sampling second-order single-OTA ΔΣ ADC, a 3-wire interface with the external module, and a programmable analog front-end, respectively. The chip has been fabricated in 0.18μm CMOS and occupies an area of only 500μm × 650μm. A 7-bit resolution is achieved for the sensor resistance ranging between 20ΚΩ and 800ΚΩ, with an overall power consumption of only 250μW.

A ultra-low-power sensor signal processor for high-performance close-loop MEMS accelerometer

This paper presents an Micro-Controller Unit (MCU) based ultra-low-power sensor signal processor design for a close-loop capacitive Micro-Electro-Mechanical Systems (MEMS) accelerometer. The proposed sensor signal processor provides basic sensor micro-system control and advanced signal processing functions, including analogue front-end configuration, digital delta-sigma modulation and decimation filtering. The accelerator design of the digital delta-sigma modulator offers good flexibility and re-configurability to enable a close-loop MEMS accelerometer with a wide dynamic range of up to 109 dB and a low nonlinearity of 0.01% from the system-level simulation. By applying ultra-low-power techniques including clock gating, power gating and ultra-low-voltage operation, a power reduction by two orders of magnitude is achieved as compared to original design in 0.18-μm CMOS technology. Simulation result shows that the digital sensor signal processing core only consumes 25.3 μW at 0.6 V in ultra low power mode.

A 0.5V 29pJ/cycle sensor node processor for intelligent sensing applications

This paper presents a sensor node processor (SNP) with optimized energy efficiency and performance for intelligent sensing through architecture-level optimization and ultra-low voltage operation with timing-error monitoring. Two typical intelligent sensing applications are demonstrated with the proposed processor, consuming 39 and 29pJ/cycle at 0.5V respectively.

A Microcontroller Interface for Embedded Non-volatile Memory on Micro Mirror Projector ASIC Calibration

This paper presents a digital controller interface for an non-volatile memory (NVM) IP (1) which is part of an embedded 8051 microprocessor system. The embedded microprocessor system is targeted to be integrated as part of a micro mirror projection ASIC for MEMS scanner control and sensing (2). The NVM memory controller interface with the storage of NVM is used to calibrate the position of micro mirror MEMS on the fly during the projection scanning mode, and store and load the configuration parameters for ASIC module initialization during power up stage. The design has been fabricated with 0.18 µm CMOS process and measurement result proves the full function of the design concept.