Jingjing Lan

HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs

A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the proposed technique eliminates the hold-time constraint and is able to deal with errors caused by infrequently activated critical paths and fast dynamic variations. It has low overhead and is applicable to general digital designs. The experimental results of applying the proposed HEPP technique to a FFT processor show 122% performance improvement or 88% energy reduction compared to the conventional worst-case design.

A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 μm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis.

Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications

This brief presents an energy- and area-efficient discrete wavelet packet transform (DWPT) processor design for power-constrained and cost-sensitive healthcare-monitoring applications. This DWPT processor employs recursive memory-shared architecture to achieve low hardware complexity while performing required arbitrary-basis DWPT decomposition. By exploiting inherent characteristics of different physiological signals through an entropy statistic engine, the DWPT processor core can be reconfigured to compute multilevel wavelet decomposition with effective time and frequency resolution. Various design techniques from algorithm to circuit levels, including reconfigurable computing, lifting scheme, dual-port pipeline processing, near-threshold operation, and clock gating, are applied to achieve energy efficiency. With a 0.18-μm CMOS technology at 0.5 V and 1 MHz, the DWPT core only consumes 26 μW for performing three-level 256-point DWPT decomposition with entropy statistic calculation. When integrated in an ARM Cortex-M0-based biomedical system-on-a-chip test platform, the DWPT processor achieves processing acceleration by three orders of magnitude and reduces energy consumption by four orders of magnitude compared with CPU-only implementations.

A 457-nW cognitive multi-functional ECG processor

In this paper, a multi-functional ECG signal processor for wearable and implantable real-time monitoring is presented. To enable extremely long-term ambulatory monitoring, several power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An on-chip low-complexity cardiac signal analysis module is proposed to realize comprehensive analysis functions. Near-threshold circuit technique is applied to the overall system. Implemented in 0.18 μm CMOS, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V supply for real-time ambulatory monitoring. Compared with existing designs, the presented ECG processor achieves the lowest power consumption.

A miniaturized heterogeneous wireless sensor node in 3DIC

In this paper, an innovative design of a miniaturized heterogeneous 3DIC-based wireless sensor node (WSN) is proposed. The design contains stacks of radio frequency (RF) die, mixed-signal die, digital die, and integrated antenna die using the through silicon via (TSV) technology. Significant enhancements to the existing 2D design and verification flow are developed to solve the critical concerns of heterogeneous 3DIC integration, including the block-level partitioning, TSV macro design, the TSV-related modeling and characterization, and physical verification. Solutions are proposed to minimize the electromagnetic interference (EMI) effects between the IC and the antenna. The size of the proposed 3DIC is only 66% as compared to a similar 2D implementation, permitting miniaturization of the complete WSN system.

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing

An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively.

A ultra-low-power sensor signal processor for high-performance close-loop MEMS accelerometer

This paper presents an Micro-Controller Unit (MCU) based ultra-low-power sensor signal processor design for a close-loop capacitive Micro-Electro-Mechanical Systems (MEMS) accelerometer. The proposed sensor signal processor provides basic sensor micro-system control and advanced signal processing functions, including analogue front-end configuration, digital delta-sigma modulation and decimation filtering. The accelerator design of the digital delta-sigma modulator offers good flexibility and re-configurability to enable a close-loop MEMS accelerometer with a wide dynamic range of up to 109 dB and a low nonlinearity of 0.01% from the system-level simulation. By applying ultra-low-power techniques including clock gating, power gating and ultra-low-voltage operation, a power reduction by two orders of magnitude is achieved as compared to original design in 0.18-μm CMOS technology. Simulation result shows that the digital sensor signal processing core only consumes 25.3 μW at 0.6 V in ultra low power mode.

An area-efficient implementation of a Message Authentication Code (MAC) algorithm for cryptographic systems

In this paper, an area-efficient hardware implementation of the lightweight Chaskey algorithm is present. The major targets of this work are resource-constrained devices. An efficient and simple design scheme is employed in order to achieve the goal. Different implementation methods of Chaskey algorithm are investigated. A hardware implementation that requires only 3334.33 gate equivalent is achieved with an operating clock frequency of 1 MHz.

A 0.5V 29pJ/cycle sensor node processor for intelligent sensing applications

This paper presents a sensor node processor (SNP) with optimized energy efficiency and performance for intelligent sensing through architecture-level optimization and ultra-low voltage operation with timing-error monitoring. Two typical intelligent sensing applications are demonstrated with the proposed processor, consuming 39 and 29pJ/cycle at 0.5V respectively.