Shang Wang

An intra-chip free-space optical interconnect

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect is a promising long term solution. However, while significant progress in optical signaling has been made in recent years, networking issues for on-chip optical interconnect still require much investigation. Taking the underlying optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of optical interconnects. In this paper, we propose and study the design of a fully distributed interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.

3-D integrated heterogeneous intra-chip free-space optical interconnect

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

This letter presents a new optical interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and -26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.

Microring-based optical pulse-train generator

This paper presents a new photonic integrated circuit, namely optical pulse-train generator, which is developed based on the transfer matrix analysis of microrings and utilizes a time-interleaved architecture. This circuit can generate multiple optical pulses sequentially from a single trigger pulse, with the timing and amplitude of each pulse determined by circuit design. Hence it can be applied in optical arbitrary waveform generation and ultrafast electro-optic modulation. A four-tap prototype pulse-train generator design is demonstrated, and the challenge of distributed optical power combining is discussed. The design techniques presented in this paper will find use in other large scale photonic integrated circuit applications.

Multilayer Coplanar Waveguide Transmission Lines Compatible with Standard Digital Silicon Technologies

On-chip transmission lines in silicon technologies suffer from the low-resistivity substrate and geometry limitations imposed by layout and metal density design rules. In this paper, we demonstrate that multilayer coplanar waveguide (MCPW) transmission lines can be utilized to overcome both problems by taking advantage of multiple metal layers available. We studied the effects of ground spacing on MCPW characteristics using electromagnetic simulations, based on process parameters from a 0.18 mum standard digital CMOS technology with 0.01 Omega-cm P+ substrate. Simulation results show that by adjusting the ground spacing, we can control the characteristics impedance, effective dielectric constant, and attenuation of MCPW lines. A test chip was designed and fabricated with MCPW, regular CPW, and microstrip lines. Measurement results verified the analysis and simulation results.

Energy efficient, reconfigurable, distributed pulse generation and detection in UWB impulse radios

Ultrafast pulse generation and detection are pivotal functions in ultra-wideband (UWB) impulse radios. This paper shows that digitally-assisted distributed circuit techniques provide an energy-efficient, reconfigurable solution for both functions, as demonstrated in two new circuits: a pulse generator that can generate reconfigurable pulse waveforms with sub-nanosecond time resolution, and a multi-GHz analog correlator that incorporates reconfigurable local template pulse generation. A UWB impulse radio was developed based on these new circuits with chip prototypes implemented in 0.18-µm standard digital CMOS. It was characterized using UWB antennas, and achieved an energy efficiency of 25-pJ/pulse for the transmitter and 190-pJ/pulse for the receiver at 250 MHz pulse rate in the measurement.

A 0.17-nJ/pulse IR-UWB receiver based on distributed pulse correlator in 0.18-µm digital CMOS

This paper presents a low power impulse-radio ultra-wideband (IR-UWB) receiver based on a reconfigurable, high speed analog correlator called distributed pulse correlator (DPC). The DPC incorporates built-in local template pulse generation, and hence significantly reduces the power consumption and circuit complexity of the analog correlation receiver. A chip prototype of the IR-UWB receiver was implemented in 0.18-µm standard digital CMOS, and achieved an energy efficiency of 0.17-nJ/pulse at 250-MHz pulse rate in the measurement.

An Energy-Efficient IR-UWB Receiver Based on Distributed Pulse Correlator

A new circuit technique called distributed pulse correlator (DPC) is proposed for pulse detection in ultra-wideband impulse radio (IR-UWB) receivers. Among several IR-UWB transceiver architectures, an analog correlation receiver has the advantages of good performance and reduced circuit complexity, but requires a correlator and a template pulse with good time resolution. To achieve both fine time resolution and low power consumption, a DPC time-interleaves multiple sampling stages operating in a power-saving pulsed mode and incorporates a built-in mechanism to generate the reconfigurable local template pulse. The operation of the DPC is theoretically analyzed and its performance evaluated, followed by a detailed discussion of its circuit implementation. A chip prototype of a 3-10-GHz analog correlation receiver employing an eight-tap, 10-GSample/s DPC was designed and fabricated in a 0.18-μm standard digital CMOS technology. In the measurement, the DPC achieves a pulse rate of 250 MHz with an energy efficiency of 40 pJ/pulse, and the whole receiver achieves an energy efficiency of 190 pJ/pulse at the 250-MHz pulse rate. The complete IR-UWB link (a transmitter, a receiver, and antennas) is also tested.

Chip-scale demonstration of 3D integrated intrachip free-space optical interconnect

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system uses point-to-point free-space optical links to construct an all-to-all intra-chip communication network. Unlike other electrical and waveguide-based optical interconnect systems, FSOI exhibits low latency, high energy efficiency, and large bandwidth density with little degradation for long distance transmission, and hence can significantly improve the performance of future many-core chips. A 1x1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. A commercial 850-nm GaAs vertical-cavity-surface-emitting-laser (VCSEL) and fabricated fused silica micro-lenses are 3-D integrated on top of the germanium substrate. At a 1.4-cm distance, the measured optical transmission loss is 5 dB and crosstalk is less than -20 dB. The electrical-to-electrical bandwidth is 3.3 GHz, limited by the VCSEL.

Experimental demonstration of microring-based optical pulse train generator

We experimentally demonstrate the concept of a microring-based optical pulse train generator that we proposed recently. A four-tap chip prototype is fabricated on SOI substrate and the measurement results verify the multiply-by-four circuit function.