Jiheon Yu

Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array

System-in-package provides highly integrated packaging with high-speed performance. Many SiP packages contain low-cost 3D stacked chips interconnected by fine wire bonds. In a high-frequency spectrum, these wire bonds can cause discontinuities causing signal degradation. This article addresses problems with wire bonding in high-frequency SiP packages and proposes design methodologies to reduce these discontinuities

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.

Advanced coreless flip-chip BGA package with high dielectric constant thin film embedded decoupling capacitor

In this paper, coreless flip-chip BGA in Amkor Technology will be introduced with two options. First option is a revised coreless substrate design with layer reduction from original core substrate design of flip-chip BGA package and the second one is the coreless substrate with high dielectric constant thin film embedded decoupling capacitor in order to improve power integrity performance. The coreless substrate was redesigned to reduce the number of layers for low-cost solution. Since the original core substrate has 12 layers (4–4–4) and the revised coreless substrate has 9 layers (8+1), the cost of flip-chip BGA substrate could be reduced. Coreless substrates will use ABF films and high dielectric constant thin film to replace core and prepreg dielectric materials and to form embedded decoupling capacitor between power/ground planes.

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78ps/sub co/ jitter and under 240mV digital noise at 500MHz, while a conventional scheme has a 172ps/sub p-p/ jitter under the same conditions.

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment

Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-out (WLFO) technology using ABF substrate can enhance routing density and provide smaller form factor with lower parasitic elements than flip-chip chip scale packages (FCCSP). Moreover, short electrical paths from die out to package out can be realized with WLFO, and the low-k ABF material provides good electrical properties for high frequency areas. In this paper, the process of WLFO using ABF substrate with laser drilling is explained and electrical parasitic elements are compared between FCCSP and WLFO using 3D simulation tools. In addition, electrical characterization of coplanar waveguide (CPW) structure and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness on millimeter wave range. Actual measurements of CPW structures are also presented.

Electrical evaluation of wafer level fan out (WLFO) package using organic substrates for microwave applications

In this paper, developments of wafer level fan-out (WLFO) technology using organic substrates, ajinomoto build-up film (ABF) with laser ablation process and buried pattern PCB, are introduced for low cost and high electrical performance not only on low frequency ranges but also microwave applications. WLFO technology using organic substrates can enhance routing density and provide smaller form factor than flip-chip chip scale packages (fcCSP). Moreover, short signal routing paths from die out to package out can be realized to improve overall electrical performance in WLFO, In this paper, the process of WLFO using ABF with laser drilling and buried-pattern PCB substrate are explained. In addition, measurements of coplanar waveguide (CPW) structure on WLFO and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness in microwave ranges.

Novel electrical modelling and measurement technique of hybrid package (FusionQuad) for characterization of RF and high speed signals

This paper discuss electrical characterization of new developed hybrid package, FusionQuad, that is converging QFN and TQFP type package to have good electrical performance with high I/O pin counts. Precise electrical modelling from wire-to-motherboard is performed by using simple organic based test die with de-embedding technique to cope with limits of assembly process. Measurements are done in the frequency domain to extract S-parameter up to 10 GHz.

3D interconnection using butterfly via for high speed and RF package design

Semiconductor markets require continuous device miniaturization while the I/O density and the frequency/speed of operation increase. Maintaining acceptable signal integrity at the system level has become more challenging than ever. Impedance control at high speeds of operation is one of the key elements of good signal integrity design. Impedance is relatively easy to control for 2D transmission lines, however becomes quite challenging for 3D structures such as wirebonds or vias. It is generally accepted that the silicone package is a major design challenge in obtaining good system level performance. In this paper, a butterfly (fan-shape) via structure is proposed for impedance control and improved shielding. Our proposed via structure is 60% ∼ 80% smaller compared to a typical through hole via therefore enables real estate saving at the package level as well.

Design trade-off for resonance reduction of multiple power planes in Super Ball Grid Array (SBGA) package

In this paper, package co-design procedure with electrical simulation supported by Amkor Technology will be described and design trade-off for effective power/ground plane design in SBGA package will be discussed. Two models of SBGA design, which has five kinds of main and sub-main power nets, are compared using 3D electromagnetic (EM) simulation tool. By comparison of both design, inevitable design trade-off for effective multiple power planes will be presented and discussed from power integrity (PI) viewpoint. The revised SBGA package design was implemented and measured to analyze plane resonances in the impedance profile of each power/ground planes according to frequencies up to 10 GHz so that the simulated self-impedances can be compared with measured results.