SeungJae Lee

Modeling of Eye-Diagram Distortion and Data-Dependent Jitter in Meander Delay Lines on High-Speed Printed Circuit Boards (PCBs) Based on a Time-Domain Even-Mode and Odd-Mode Analysis

Crosstalk induced in a meander delay line produces a significant amount of waveform distortion and data-dependent jitter at the output port. This paper introduces an interpretation of the eye-diagram distortion and the jitter generation mechanism based on a time-domain even- and odd-mode analysis of a coupled transmission line structure. From the proposed analysis, this paper proposes jitter-estimation equations for both the short and long unit line delay cases. The eye-diagram distortion and timing jitter are predicted and estimated, respectively. In order to verify the jitter-estimation equations, a series of microstrip-type printed circuit board test vehicles with the meander delay line are fabricated and tested. The measured jitter shows good agreement with the proposed jitter-estimation equations.

Advanced coreless flip-chip BGA package with high dielectric constant thin film embedded decoupling capacitor

In this paper, coreless flip-chip BGA in Amkor Technology will be introduced with two options. First option is a revised coreless substrate design with layer reduction from original core substrate design of flip-chip BGA package and the second one is the coreless substrate with high dielectric constant thin film embedded decoupling capacitor in order to improve power integrity performance. The coreless substrate was redesigned to reduce the number of layers for low-cost solution. Since the original core substrate has 12 layers (4–4–4) and the revised coreless substrate has 9 layers (8+1), the cost of flip-chip BGA substrate could be reduced. Coreless substrates will use ABF films and high dielectric constant thin film to replace core and prepreg dielectric materials and to form embedded decoupling capacitor between power/ground planes.

Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-out (WLFO) technology using ABF substrate can enhance routing density and provide smaller form factor with lower parasitic elements than flip-chip chip scale packages (FCCSP). Moreover, short electrical paths from die out to package out can be realized with WLFO, and the low-k ABF material provides good electrical properties for high frequency areas. In this paper, the process of WLFO using ABF substrate with laser drilling is explained and electrical parasitic elements are compared between FCCSP and WLFO using 3D simulation tools. In addition, electrical characterization of coplanar waveguide (CPW) structure and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness on millimeter wave range. Actual measurements of CPW structures are also presented.

Electrical evaluation of wafer level fan out (WLFO) package using organic substrates for microwave applications

In this paper, developments of wafer level fan-out (WLFO) technology using organic substrates, ajinomoto build-up film (ABF) with laser ablation process and buried pattern PCB, are introduced for low cost and high electrical performance not only on low frequency ranges but also microwave applications. WLFO technology using organic substrates can enhance routing density and provide smaller form factor than flip-chip chip scale packages (fcCSP). Moreover, short signal routing paths from die out to package out can be realized to improve overall electrical performance in WLFO, In this paper, the process of WLFO using ABF with laser drilling and buried-pattern PCB substrate are explained. In addition, measurements of coplanar waveguide (CPW) structure on WLFO and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness in microwave ranges.

Novel electrical modelling and measurement technique of hybrid package (FusionQuad) for characterization of RF and high speed signals

This paper discuss electrical characterization of new developed hybrid package, FusionQuad, that is converging QFN and TQFP type package to have good electrical performance with high I/O pin counts. Precise electrical modelling from wire-to-motherboard is performed by using simple organic based test die with de-embedding technique to cope with limits of assembly process. Measurements are done in the frequency domain to extract S-parameter up to 10 GHz.

3D interconnection using butterfly via for high speed and RF package design

Semiconductor markets require continuous device miniaturization while the I/O density and the frequency/speed of operation increase. Maintaining acceptable signal integrity at the system level has become more challenging than ever. Impedance control at high speeds of operation is one of the key elements of good signal integrity design. Impedance is relatively easy to control for 2D transmission lines, however becomes quite challenging for 3D structures such as wirebonds or vias. It is generally accepted that the silicone package is a major design challenge in obtaining good system level performance. In this paper, a butterfly (fan-shape) via structure is proposed for impedance control and improved shielding. Our proposed via structure is 60% ∼ 80% smaller compared to a typical through hole via therefore enables real estate saving at the package level as well.

Design trade-off for resonance reduction of multiple power planes in Super Ball Grid Array (SBGA) package

In this paper, package co-design procedure with electrical simulation supported by Amkor Technology will be described and design trade-off for effective power/ground plane design in SBGA package will be discussed. Two models of SBGA design, which has five kinds of main and sub-main power nets, are compared using 3D electromagnetic (EM) simulation tool. By comparison of both design, inevitable design trade-off for effective multiple power planes will be presented and discussed from power integrity (PI) viewpoint. The revised SBGA package design was implemented and measured to analyze plane resonances in the impedance profile of each power/ground planes according to frequencies up to 10 GHz so that the simulated self-impedances can be compared with measured results.