Jim Snow

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V/sub T/ of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I/sub on/-I/sub off/ of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V/sub D/=l .3V for an EOT of 1.8nm.

Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

Effect of Dissolved Oxygen for Advanced Wet Processing

of these new materials have necessitated the evaluation of new chemicals and processing methods. The control of the Dissolved Oxygen (DO) concentration to suppress Cu corrosion is well established in BEOL processing and likewise in order to achieve a hydrophobic surface after pre-epi cleaning in FEOL surface preparation [2].

Wet Etching Behavior of Poly-Si in TMAH Solution

Since Tetramethylammonium Hydroxide (TMAH) became widely used as a silicon etchant, e.g. the dummy gate removal for gate-last approach (RMG) [1, or Si fin formation on FinFET [, some careful preparations and optimizations have required implementation. These adaptations have involved not only chemical-related issues, but also hardware-related in order to satisfy the necessary process performance.

The Effect of Rinsing a Germanium Surface after Wet Chemical Treatment

The impact of rinsing liquid for Germanium surface after wet chemical treatment is described. The different Ge loss after processing with different rinse (UPW and CO2 water) were determined and the different surface morphologies on the Ge surface after processing with different chemicals (AOM, HF and HCl) were determined by XPS. It was found that the investigation of surface morphology after chemical treatment is necessary to understand the rinse effect and the results showed the CO2 water rinse can decrease and suppress Ge loss at chemical treatment

Applicable Solvent Photoresist Strip Process for High-K/Metal Gate

In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.