Jim Svensson

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation

Carrier aggregation (CA) is introduced in 3GPP LTE Rel-10 [1] to meet the demand for further increased bitrates. While LTE Rel-10 supports simultaneous reception of two carriers either in contiguous intra-band or in inter-band CA configuration, the upcoming LTE Rel-11 will add support for non-contiguous (NC) carriers within bands. Supporting NC CA in handsets is a demanding challenge for several reasons. Foremost, the total bandwidth spanned by the carriers may be several times the bandwidth of the individual carriers, possibly spanning an entire band with interfering signals between desired carriers. Furthermore, the distance between TX and RX carriers will vary and worse, may be much smaller than the fixed duplex distance for LTE Rel-8 and W-CDMA single carrier operation [2-5].

Low-Complex ICI Cancellation for Improving Doppler Performance in OFDM Systems

A combination of receiver windowing and inter-carrier interference (ICI) canceling is proposed for improving the Doppler performance of orthogonal frequency division multiplex (OFDM) systems. The windowing reduces the ICI, and also reduces the required number of canceled bins. The effect of windowing is analytically derived, and bounds are given on the possible gain that can be obtained. Since successful ICI cancellation relies on that the channel can be accurately estimated, the paper also give examples for how different one-dimensional and two-dimensional channel estimators can be expected to work for various Doppler spread and delay spread of the channel. To verify that the proposed approach for ICI canceling works, as well as studying the impact of channel estimation errors, simulations are performed using the key parameters of DVB-H. As a result it is found that with proper channel estimation, windowing but no ICI cancellation can increase the allowed Doppler by 20%, ICI cancellation but no windowing can also increase the allowed Doppler by 20%, and if both windowing and ICI cancellation are used, the allowed Doppler can increase by more than 40%.

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers, clocked by a ring-oscillator based phase-locked loop and driven by sequencers that represent thermometer-coded oversampled sinusoidal LO waveforms. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance correction. The complex IF mixer supports reception of two carriers with up to 65 MHz separation using 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.74 mm2, draws 26 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

A 4.75–34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS

A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation is presented. It has a 0.4 dB passband ripple, reconfigurable bandwidth (4.75-34.75 MHz), automatic RC tuning, and IQ-mismatch correction. The noise power spectral density referred to the filter input is 3.8pA/√Hz at 90 % of the bandwidth. The output referred third order intercept point (OIP3) is 39.4 dBm for a two tone input at 47 MHz and 70 MHz. By digitally controlling the passive circuit elements of the filter, the frequency dependent gain and phase IQ mismatch can be reduced, resulting in a remaining gain error below 0.35 % and a maximum phase error of 0.23 degrees. After calibration, the IQ matching is sufficient for a mean receiver image-rejection ratio of more than 60 dB. The current consumption is 39 mA from a 1.2 V supply.

Some Results on Implementing Low-Complex ICI Cancellation for DVB-H

A combination of receiver windowing and inter-carrier interference (ICI) canceling is proposed for improving the Doppler frequency performance of a DVB-H receiver. The windowing reduces the ICI, and enables ICI cancellation of low complexity to give substantial improvements. Bounds for the possible improvements of ICI cancellation are presented and compared to results from both simulations and measurements on a DVB-H prototype. The obtained improvements from windowing agree well with that predicted by theory, whereas the gain from ICI cancellation is considerably smaller. This is primarily due to non-ideal channel estimation, which also is discussed. Although the measured performance for ICI cancellation is far from that theoretically possible, the gain in what Doppler frequency can be handled is more than 40%.

Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers individually driven by a sequencer to represent an oversampled sinusoidal LO waveform. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance calibration. The complex IF mixer supports reception of two carriers with up to 65 MHz separation with 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.48 mm2, draws 19.7 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation

A design methodology based on close interaction between algorithm development and analog implementation is used to develop a configurable complex IF receiver front-end with 60 dB image rejection ratio (IRR). To achieve this high IRR, calibration of the IQ-mismatch is needed. By using statistical link simulations, feasible analog components for calibration are determined and the corresponding required calibration ranges and resolutions are found. In a wideband system, as considered here, both frequency dependent and frequency independent IQ-mismatch are treated. The results from the statistical simulations are based on optimum calibration parameters, and agree very well with those achieved with the implemented algorithm, confirming that 60 dB image rejection ratio is achieved.

Nex generation digital front-end for multi-standard concurrent reception

This article presents an architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals. A main focus is placed in flexibility, scalability and concurrency. The architecture is capable of detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. The proposed receiver is fabricated in a 65 nm CMOS low power high-VT cell technology in a die size of 5mm2. The synchronization engine has been measured at 1.2V and reports an average power consumption of 1.9mW during IEEE 802.11 (WLAN) reception and 1.6mW during configuration, while running at 10 MHz.

A new digital front-end for flexible reception in software defined radio

Future mobile terminals are expected to support an ever increasing number of Radio Access Technologies (RAT) concurrently. This imposes a challenge to terminal designers already today. Software Defined Radio (SDR) solutions are a compelling alternative to address this issue in the digital baseband, given its high flexibility and low Non-Recurring Engineering (NRE) cost. However, the challenge still remains in the Digital Front-End (DFE), where many operations are too complex or energy hungry to be implemented as software instructions. Thus, new architectures are needed to feed the SDR digital baseband while keeping complexity and energy consumption at bay. In this article the architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals is presented. The flexibility needed for multi-standard support is demonstrated by detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. Moreover, the proposed architecture has been fabricated in a 65nm CMOS low power high-VT cell technology in a die size of 5mm2. The core module of the DFE-Rx, the synchronization engine, has been measured at 1.2V and reports an average power consumption of 1.9mW during Wireless Local Area Network (WLAN) reception and 1.6mW during configuration, while running at 10MHz.