Roland Strandberg

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution

The future of cellular radio ICs lies in the integration of an ever-increasing number of bands and channel bandwidths. Figure 21.2.1 shows the block diagram of our transceiver, together with the associated discrete front-end components. The transceiver supports 4 EDGE bands and 9 WCDMA bands (I-VI and VIII-X), while the radio can be configured to simultaneously support the 4 EDGE bands and up to 5 WCDMA bands: 3 high bands (HB) and 2 low bands (LB). The RX is a SAW-less homodyne composed of a main RX and a diversity RX. To reduce package complexity with so many bands, we chose to minimize the number of ports by using single-ended RF interfaces for both RX and TX. This saves several package pins, but requires careful attention to grounding. The main RX has 8 LNA ports and the diversity RX has 5, with some LNAs supporting multiple bands. On the TX side, 2 ports are used for all EDGE bands and 4 for the WCDMA bands.

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation

Carrier aggregation (CA) is introduced in 3GPP LTE Rel-10 [1] to meet the demand for further increased bitrates. While LTE Rel-10 supports simultaneous reception of two carriers either in contiguous intra-band or in inter-band CA configuration, the upcoming LTE Rel-11 will add support for non-contiguous (NC) carriers within bands. Supporting NC CA in handsets is a demanding challenge for several reasons. Foremost, the total bandwidth spanned by the carriers may be several times the bandwidth of the individual carriers, possibly spanning an entire band with interfering signals between desired carriers. Furthermore, the distance between TX and RX carriers will vary and worse, may be much smaller than the fixed duplex distance for LTE Rel-8 and W-CDMA single carrier operation [2-5].

Single input current-sensing differential logic (SCSDL)

A new novel single input current-sensing differential logic (SCSDL) is proposed. The SCSDL is flexible-in particular high input Boolean logic functions can be implemented with low complexity, area consumption, time delay, and power consumption. The first part of the area saving comes from the remarkable reduction of wiring; the other part comes from the very low number of transistors needed to implement a complex Boolean function, compared with other types of logic (e.g. CRDL, CSDL, DCVSL, static logic). Since this logic relies on comparison of currents in two branches, mismatch could ruin the function. The yield of the logic is good for a high performance process referred to mismatch.

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers, clocked by a ring-oscillator based phase-locked loop and driven by sequencers that represent thermometer-coded oversampled sinusoidal LO waveforms. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance correction. The complex IF mixer supports reception of two carriers with up to 65 MHz separation using 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.74 mm2, draws 26 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

A 4.75–34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS

A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation is presented. It has a 0.4 dB passband ripple, reconfigurable bandwidth (4.75-34.75 MHz), automatic RC tuning, and IQ-mismatch correction. The noise power spectral density referred to the filter input is 3.8pA/√Hz at 90 % of the bandwidth. The output referred third order intercept point (OIP3) is 39.4 dBm for a two tone input at 47 MHz and 70 MHz. By digitally controlling the passive circuit elements of the filter, the frequency dependent gain and phase IQ mismatch can be reduced, resulting in a remaining gain error below 0.35 % and a maximum phase error of 0.23 degrees. After calibration, the IQ matching is sufficient for a mean receiver image-rejection ratio of more than 60 dB. The current consumption is 39 mA from a 1.2 V supply.

Bandwidth considerations for a CALLUM transmitter architecture

This article presents an investigation of the combined analog locked loop universal modulator (CALLUM) linear transmitter architecture. A simple approximate formula is derived, linking the instantaneous frequency of the CALLUM signals to the modulation depth of the information signal. Furthermore, the effect of the frequency mismatch between the VCOs present in the CALLUM architecture is examined, and the need for frequency synchronization via a phase locked loop is discussed.

Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers individually driven by a sequencer to represent an oversampled sinusoidal LO waveform. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance calibration. The complex IF mixer supports reception of two carriers with up to 65 MHz separation with 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.48 mm2, draws 19.7 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

High-Level Design Flow for All-Digital PLLs

Deep-submicrometer CMOS processes are not suitable for traditional analog circuit design but they provide new opportunities of integrating complex digital functions. Within RF wireless communications, frequency synthesis stands out as a fundamental feature and novel digital solutions have been suggested for its implementation. Moving from an existing model, the goal of this paper is to outline the steps of a high-level approach to the design of an all-digital phase-locked loop (ADPLL)

Spectrum emission considerations for baseband-modeled CALLUM architectures

Linear transmitters based on combined analog locked loop universal modulator (CALLUM) architectures are attractive, as they promise both high efficiency and high linearity. To date, it has not been possible to analyze a CALLUM transmitter as a linear feedback network due to the nonlinear nature of the control equations governing it. The main purpose of this paper has been the derivation of a linearized model for the control equations, which enables the use of linear network theory in the study of CALLUM. In particular, it can be used to analyze the stability and maximize the bandwidth of the system. Simulation examples are presented on how three different CALLUM architectures behave for enhanced data rates for global system for mobile communications evolution and wide-band code-division multiple-access signals. In addition, we have considered the effects of loop time delay, which is the ultimate limiting factor for all feedback-based linear transmitter architectures, particularly for large bandwidths. Finally, it is shown how frequency compensation of the feedback loop improves insensitivity to the loop time delay

Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation

A design methodology based on close interaction between algorithm development and analog implementation is used to develop a configurable complex IF receiver front-end with 60 dB image rejection ratio (IRR). To achieve this high IRR, calibration of the IQ-mismatch is needed. By using statistical link simulations, feasible analog components for calibration are determined and the corresponding required calibration ranges and resolutions are found. In a wideband system, as considered here, both frequency dependent and frequency independent IQ-mismatch are treated. The results from the statistical simulations are based on optimum calibration parameters, and agree very well with those achieved with the implemented algorithm, confirming that 60 dB image rejection ratio is achieved.