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Dive into the research topics where Jin-Bum Kim is active.

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Featured researches published by Jin-Bum Kim.


symposium on vlsi technology | 2003

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

T. Park; S. Choi; Dohyun Lee; Jae-yoon Yoo; Byeong-Chan Lee; Jin-Bum Kim; Choong-Ho Lee; K.K. Chi; Sug-hun Hong; S.J. Hynn; Yun-Seung Shin; Jungin Han; In-sung Park; U-In Chung; Joo Tae Moon; E. Yoon; Jong-Ho Lee

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.


symposium on vlsi technology | 1999

A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

T. Park; Jin-Bum Kim; K.W. Park; Hyun-Suk Lee; H.B. Shin; Yong-Il Kim; Moon-han Park; Hyuk Kang; Myoung-Bum Lee

A novel simple shallow trench isolation technology, SSTI, has been developed. SSTI consists of direct trench etching masked only with the photoresist, trench oxidation, liner SiN deposition, CVD oxide trench fill, densification, and high selectivity CMP. CMP stops at the liner SiN with a residual SiN thickness range of less than 2 nm and without micro-scratching. High selectivity CMP eliminates the field recess variation which is one of the drawbacks of conventional STI. SSTI is a promising candidate for future isolation technology.


ACS Applied Materials & Interfaces | 2017

Chemically Homogeneous and Thermally Robust Ni1–xPtxSi Film Formed Under a Non-Equilibrium Melting/Quenching Condition

Jin-Bum Kim; Seongheum Choi; Taejin Park; Jinyong Kim; Chul-Sung Kim; Taeho Cha; Hyangsook Lee; Eunha Lee; Jung Yeon Won; Hyung-Ik Lee; Sang-Jin Hyun; Sunjung Kim; Dong-Suk Shin; Yihwan Kim; Kee-Won Kwon; Hyoungsub Kim

To synthesize a thermally robust Ni1-xPtxSi film suitable for ultrashallow junctions in advanced metal-oxide-semiconductor field-effect transistors, we used a continuous laser beam to carry out millisecond annealing (MSA) on a preformed Ni-rich silicide film at a local surface temperature above 1000 °C while heating the substrate to initiate a phase transition. The melting and quenching process by this unique high-temperature MSA process formed a Ni1-xPtxSi film with homogeneous Pt distribution across the entire film thickness. After additional substantial thermal treatment up to 800 °C, the noble Ni1-xPtxSi film maintained a low-resistive phase without agglomeration and even exhibited interface flattening with the underlying Si substrate.


RSC Advances | 2017

Atomic layer deposition of Al2O3 on MoS2, WS2, WSe2, and h-BN: surface coverage and adsorption energy

Taejin Park; Hoijoon Kim; Mirine Leem; Wonsik Ahn; Seongheum Choi; Jin-Bum Kim; Joon Uh; Kee-Won Kwon; Seong-Jun Jeong; Seongjun Park; Yunseok Kim; Hyoungsub Kim

Uniform deposition of high-k dielectrics on two-dimensional (2D) crystals is highly desirable for their use in future nano-electronic devices. Here, the surface coverage of the Al2O3 films grown by atomic layer deposition (ALD) was investigated on mechanically-exfoliated MoS2, WS2, WSe2, and h-BN flakes for exploring the deposition kinetics of the Al2O3 films on the 2D crystals. The film coverage followed a decreasing order of WSe2 > WS2 > MoS2 > h-BN, which was mainly determined by the ALD temperature and adsorption energy (Eads) of the ALD precursor (trimethyl-aluminum) during the initial ALD cycles. The obtained |Eads| values of the precursor on the 2D crystals corresponded well to a van der Waals physisorption energy of 0.05–0.26 eV. Furthermore, the magnitude of the extracted Eads values showed a strong dependence on the induced dipole polarizability of the 2D crystals. The obtained results demonstrate that the surface coverage of the ALD high-k dielectrics can be modulated by choosing the types of the 2D substrates, and could provide a pathway for the integration of high-k dielectrics in 2D crystal-based nano-electronic devices.


Archive | 2012

Electrolyte for lithium secondary battery and lithium secondary battery including the same

Jin Sung Kim; Ha Young Lee; Jin-Bum Kim; Yongshik Kim; Narae Park; Myungkuk Patk


Archive | 2010

Method of Manufacturing Semiconductor Device Having Stress Creating Layer

Jin-Bum Kim; Wook-Je Kim; Yu-gyun Shin; Kwanheum Lee; Sun-Ghil Lee


Archive | 2011

Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers

Jin-Bum Kim; Si-Young Choi; Hyung-Ik Lee; Ki-Hong Kim; Yong-Koo Kyoung


Archive | 2007

Electrolyte for high voltage lithium rechargeable battery and high voltage lithium rechargeable battery employing the same

Yongshik Kim; Jin-Bum Kim; Jinsung Kim; Narae Park


Archive | 2009

Semiconductor devices having Si and SiGe epitaxial layers

Jin-Bum Kim; Si-Young Choi; Hyung-Ik Lee; Ki-Hong Kim; Yong-Koo Kyoung


Archive | 2009

Electrolyte and lithium ion secondary battery comprising the same

Jinsung Kim; Narae Park; Jin-Hyunk Lim; Su-Hee Han; Jin-Bum Kim; Jungkang Oh

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