Young-pil Kim

Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity

LEG (laser-induced epitaxial growth) process has been proposed to obtain the single c-Si layer over oxide and successfully demonstrated with cell-stacked high density SRAM. With LEG process, the energy density of laser beam and the seed formation are the key factors to determine the crystal quality of Si layer on oxide. CMOSFETs on Si film prepared by LEG process have excellent behaviors in terms of both performance and its variations. It is found that high density LEG SRAMs with stacked cell transistor have fully worked with the lowest stand-by current of less than 0.3 uA/Mb to date. LEG process is believed to be a promising technology for providing the high quality Si channel layer to the stacked memory devices.

Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM

For the first time, a highly manufacturable fin-channel array transistor (FCAT) on a bulk Si substrate has been successfully integrated in a 512 M density DRAM with sub-70nm technology. The FCAT shows an excellent short channel behavior, such as extremely low subthreshold swing (SS) (/spl sim/75mV/dec) and DIBL (/spl sim/13mV/V), and a high cell transistor drive current with remarkably low subthreshold leakage current (/spl sim/0.2fA/cell).

Lateral integration of partially insulated and bulk MOSFETs using partial SOI process

We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.

Junction leakage current degradation under the off-state bias-temperature stress: a new reliability assessment method for high-density DRAMs

A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed.

Reliability degradation of high density DRAM cell transistor junction leakage current induced by band-to-defect tunneling under the off-state bias-temperature stress

The band-to-defect tunneling (BDT) induced junction leakage current of high density DRAM cell transistors under off-state bias-temperature (B-T) stress was studied in detail for the first time. It was found that the BDT leakage current is most critical for limiting the cell transistor scaling. The new off-state B-T stress was proven to be a very effective reliability assessment tool for leakage current degradation of the DRAM cell transistor. It was also found to be useful for assessing reliability degradation of future high density DRAMs.

A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)

The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT) to suppress body effect of conventional RCAT and improve current drivability in DRAM cell. The Pi-RCAT demonstrated superior characteristics in body effect, subthreshold slope (SW) and higher current drivability with comparable Ion-Ioff characteristics in comparison with conventional RCAT. Furthermore, in the partially-insulated-STI (Pi-STI) of core and peripheral structure formed simultaneously, well isolation characteristic is improved remarkably due to increase of effective isolation path. In this paper, Pi-RCAT is proved to be effective for the scalability and drivability of RCAT, and Pi-STI is suitable for the improvement of chip shrinkage efficiency.

An array cell transistor test structure for the leakage current analysis of stacked capacitor DRAMs with diagonal cell scheme

A new test structure for a stacked capacitor DRAM cell transistors with a diagonal active-area was developed to analyze the leakage current characteristics of the cell transistors. The leakage current components of the low power DRAMs with different retention fail distributions was investigated in detail using the test structure, and the important aspect of the sub-threshold leakage component was discussed for below 0.11 /spl mu/m DRAM cell transistors.

Comparison of finite element stress simulation with X-ray measurement for the aluminum conductors with different passivation topography

This paper evaluates the dependence of the thermal stresses of aluminum conductors and Si02 layers deposited by several different processes using the finite element method(FEM) and topography simulation. The results of topography simulation for four different deposition processes agree well with scanning electron microscopes and subsequent FEM stress simulations are compared with X-ray diffraction measurement data. Simulation results show that the different stresses are created in aluminum lines from different passivation processes. Especially, the stresses of aluminum lines decrease as the encapsulation of aluminum conductors by the oxide layer with void profiles decrease. Through this topography simulation followed by stress simulations for different deposition processes, we can systematically define the failure mechanisms of aluminum lines for various passivation processes.

The effect of residual tensile stress on electromigration lifetime of metal lines passivated by various oxides

Residual stress of metal interconnects passivated by four different oxides was precisely measured by X-ray diffraction method, and the effect of this stress on electromigration (EM) lifetime of the Al-Cu lines was investigated. The EM lifetime was not a monotonous function of the residual stress; instead, it increased with the stress at low stress region, but decreased at the higher stress region. The stress of 200-250 MPa, which is the mid-value between compressive and tensile yield strength of the Al-Cu lines, provided the maximum EM lifetime. This result gives an experimental support to a theoretical calculation on the stress evolution due to EM and a guideline to maximize the EM lifetime for applications.