Hee-Bom Kim

Optical lithography simulation considering impact of mask errors

With smaller features sizes and higher pattern densities on high-end mask for DUV lithography, pattern fidelity on mask features becomes essential for optical proximity correction (OPC) performance. But some degree of corner rounding on the mask is inevitable even using the latest writing tool. The corner rounding radius on mask is mainly determined by the resolution of writing tool, mask resist process and chrome etching process following. In this paper, we will first discuss corner rounding impact for two-dimensional pattern applied OPC. Secondly modeling mask patterning process by applying diffused aerial image model (DAIM). Thirdly we will compare mask simulation results and mask SEM image for various mask masking process. Finally, we will examine a new simulation method to enhance the accuracy of wafer patterning simulation by using not CAD layout but mask layout extracted from mask patterning simulation.

Exposure latitude analysis for dense line and space patterns by using diffused aerial image model

Ultimate limitation of lithography has been studied by using the diffused aerial image model (DAIM). Assuming that only the 0th and 1st order diffraction beams in the off-axis illumination technique contribute to the resist patterns, aerial image is calculated for dense line and space patterns. And then DAIM is applied to achieve final image. By using this diffused aerial image, exposure latitude and mask error effect can be analyzed quantitatively. In the case of perfect image, which can be achieved from, for example, diffraction free x-ray lithography or electron beam lithography without Coulomb repulsion and back scattering effect, same approaches are possible to get the exposure latitude and mask error effect. Under the validation of DAIM, most important parameter, which characterizes dense L/S patterns, is the diffusion length of acid. In order to realize sub-o.1 micrometers pattern with enough process margins, it is required to enlarge exposure latitude and to reduce mask error effect. Therefore, reducing h acid diffusion length of chemical amplification resist (CAR) or new conceptual resist instead of CAR will be needed for sub-0.1 micrometers era.

Accuracy of diffused aerial image model for full-chip-level optical proximity correction

Recently, the miniaturization of the design rule of memory devices pushes the minimum feature sizes down to sub- wavelengths of the exposure tools. The design of a memory device comprises not only the dense patterns with critical small size in the cell region but also the random patterns in the peripheral region; the latter also need sub- wavelength lithography technology as well as the former. And the optical proximity correction (OPC) has been strongly required for the random patterns in the peripheral region where the same energy is exposed as in the cell region. Therefore, the high accuracy of simulation model used in the OPC is necessary for the full chip OPC tools. However traditional aerial image simulation has a limitation to the application due to its lack of accuracy because it does not take into account a resist process. We introduced novel lithography simulation model in 1998, which describes resist process by diffusion and chemically amplification function.

Comparative study of chromeless and attenuated phase-shift mask for 0.3-k1 ArF lithography of DRAM

The purpose of this paper is to do the direct comparison of between the novel chrome-less phase shift mask (CLM), which is suggest by Chen et. al. recently, and attenuated phase shift mask which has been in the main stream of DRAM lithography. Our study is focused on the question of whether the CLM technology has a potential advantages compared with attenuated PSM, so as to substitute the position of it in 0.3 k1 lithography era of DRAM. Firstly, some basic characteristics of both masks are studied, that is intensity distribution of diffraction orders and optical proximity effect etc. And then mask layouts are optimized through the resist patterning simulation for various critical layers of DRAM with CLM and attenuated PSM, respectively. Resolution performances such as exposure latitude and DOF margin and mask error enhancing factor etc. are compared through the simulations and experiments. In addition, it is also studied in the point of mask manufacturing of CLM such as phase control issues, defect printability, mask polarity, and so forth.

0.33-k1 ArF lithography for 100-nm DRAM

We have evaluated 0.33k1 ArF lithography using 0.63NA scanner to develop 100 nm DRAM. ArF resist problems were resist pattern shrinkage during CD SEM measurement, resist pattern collapse during wet development and poor etch resistance. Off-Site Measurement (OSM) method has been developed for decreasing pattern shrinkage. With OSM method, 8nm of CD shrinkage was down to 2nm for 100nm L/S patterns. We have found a proper BARC material that prevents resist patterns falling down. Lack of etch resistance was compensated by hard mask. With W/SiN hard mask, acrylate- type resist patterns were transferred well into W/poly-Si gate patterns. We have simulated process window of critical DRAM cell patterns (isolation, gate, bit line contact, storage node) in the simple off-axis illumination (OAI) and optical proximity correction (OPC) conditions based on single exposure. Simulation results were verified by lithography tests and it turned out that 0.33k1 process was possible with exposure latitude of above 10% and focus latitude of more than 0.4 micrometers . 0.33k1 ArF lithography was successfully implemented into 100 nm DRAM with CD uniformity of 10nm (3 (sigma) ) and overlay accuracy of 30 nm (mean +3 (sigma) ). We have also evaluated double exposure technique using dipole illumination targeting 90 nm in order to see the possibility of 0.29k1 process. 0.29k1 process was also likely to be possible, although some specific improvements were recommended for the wider process window. From the simulation and resist patterning results, we believe that 0.85 NA lens will be able to extend ArF lithography into 75 nm by single exposure technology using crosspole illumination (0.33k1 process) and 65 nm by double exposure technology using dipole and crosspole illumination (0.29k1 process).

Double-exposure strategy using OPC and simulation and the performance on wafer with sub-0.10-μm design rule in ArF lithography

As the pattern size becomes smaller, double or multi exposure is required unless the epochal solutions for overcoming the limits of present lithography system do appear or are discovered. ArF DET (double exposure technology) strategy based on manual OPC with in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method to extend the limitation of current lithography. HOST requires no additional procedures and separate layout optimizations of each region in terms of OPC are enough. Furthermore, it is possible to change illumination condition of each region and the overlap between two regions with ease. The results from the simulation are pattern size and profile of each condition according to the defous and misregistration. 0.63 NA ArF Scanner and Clariant resist is used for wafer process. The resist was coated on Clariant organic BARC using 0.24 um thickness. Dipole illumination for cell region and annular illumination for peripheral region are used. Cell region contains 0.20 um pitch duty pattern and peripheral region 0.24 um pitch duty pattern. The boundary of two regions is investigated in view of validity of stitching itself. The layout of reticles used as the cell and peripheral region are optimized by OPC, respectively and then, additional OPC was treated to the boundary, i.e., stitching area to compensate the cross term of the boundary caused by separate and independent optimization with OPC in the cell and the peripheral regime. The final patterns were acquired by defining the cell at first and the peripheral region secondly with different defocus and registration in respect to the cell. The actual data on wafer are presented according to defocus and one regions overlay offset relatively to the other region. And the outstanding matching between simulation results and in-line data are shown. Lithography process window for stable patterning is thoroughly investigated in view of depth of focus, energy latitude, registration between two stitched regions and stitching itself in the boundary. It is found from the experiment that total DOF of DE (double exposure) is 0.5 um and the total EL of DE is 10.0% in this paper. At present, it is very difficult to ensure stable process margin for the sub-0.10 um patterning. But there is a promising technology called stitching with special optimization. In addition, this technology will be nominated as an eternal candidate process whenever our lithography is in the adversity at the limits of his days.

Defect printability and specification of ArF mask in repeating feature

As ArF process will be substituted for KrF process at below 0.13 um node, it is time to study CD budget of mask error in ArF lithography. The purpose of this study is to investigate printability of ArF mask defects and corresponding effective specification in repeating cell. Mask defects in regularly repeated pattern were classified as point defect, line defect, and are defect, for conveniences sake, according to their sizes and lithographic explanations. Based on such classification, test reticle (ArF attenuated PSM) was manufactured in our captive mask shop. After exposed at a nominal dose and e-beam cured, each defects was inspected to extract effective specification for ArF process. MNPD (maximum non-printable defect) sizes of various duty patterns were manifested in point defect. In line defect and area defect, as the base pattern CD and duty ratio changed, the slope (MEF) of linear fitting was obtained. Maximum CD deviation from mean CD could be calculated from it. Mask CD budget was considered as 50% of total wafer CD error (10% of target) for mask spec generation. Experimental result was compared with DAIM (diffused aerial image model)-based simulation result because experiment had the error that arose from e-beam curing.

The double exposure strategy using OPC and simulation and the performance on wafer with sub-0.10 /spl mu/m design rule in ArF lithography

Lately, photolithography is seen as the bottleneck to sub-0.1 /spl mu/m patterning. Namely, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as in the cell region into the resolution limit of exposure tools. Although it is common to use single exposure for lithographic layer formation, an ArF double exposure technique (DET) strategy, based on manual OPC and an in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method for overcoming the limit and its results on wafer are shown. The in-house simulation tool used in this paper can predict the wafer pattern and process margin of a lithographic layer and shows good validity in the ArF process.

Application of full-chip level optical proximity correction to memory device with sub-0.10-μm design rule and ArF lithography

Recently, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as cell region to the resolution limit of exposure tools. Therefore it is necessary to apply optical proximity correction (OPC) not only to the patterns in cell region but also to those in peripheral region. It is impossible to apply manual OPC method in peripheral region. Because the peripheral region is composed of random patterns with large data volume, and it takes too long execution time with manual OPC. For random pattern OPC in peripheral region, automatic OPC tool is required. Now for the automatic OPC tool, model-based and rule-based methods are developed for the commercial use. In this paper, the effectively applicable process is discussed using model-based method in automatic OPC at the sub-0.10 micrometer design rule in ArF lithography. For the application of automatic OPC tool at the design rule of sub-0.10 micrometer and ArF process in memory devices the following problem should be cleared. In small size of design rule, we should consider not only pattern fidelity but also process margin such as depth of focus (DOF) and exposure latitude (EL) at the cell OPC. But automatic OPC tool is insufficient to be applied for cell region OPC, because it considers not process margin but pattern fidelity and it has low accuracy using much approximation model to reduce layout correction time. To solve this problem, we suggest a full chip OPC process using both automatic OPC tool and the manual OPC method using the novel lithography simulation model (Diffused Aerial Image Model, DAIM). DAIM is available to predict wafer pattern and process margin of cell, its accuracy is verified in ArF process as in KrF process. We could see small standard deviation error between experiment and DAIM in ArF process using various line or space patterns, which is about 9 nm at binary intensity mask (BIM). So the manual OPC with DAIM resulted in the wide process margin and good pattern fidelity overcoming the limitation of automatic OPC tool. However it is necessary to correlate energy level of DAIM for cell region OPC with that of the model in the automatic OPC tool for peripheral region OPC, because cell and peripheral region are exposed with the same exposure dose in stepper or scanner. In case of ArF process, we could see the small difference of energy level and standard deviation error, which is about 1.4%, 2 nm at BIM and 6.3%, 3 nm at half-tone phase shift mask (PSM), between DAIM and automatic OPC tool. As the result of using DAIM and automatic OPC tool simultaneously at full chip OPC, we could see improved results from cell to peripheral region at the sub-0.10 micrometer design rule in ArF lithography.

Potentialities of sub-100-nm optical lithography of alternating and phase-edge phase-shift mask for ArF lithography

The patterning potentialities of sub-100nm pattern for ArF lithography was evaluated with conventional alternating PSM (alt-PSM) for dense lines and spaces (L/S) and phase edge PSM (PE-PSM) for isolated lines of memory device. In dense L/S pattern,110nm pattern was defined with relatively small depth of focus(DOF) window(~ 0.2 ?m) due to phase error of mask. As pattern sizes was changed from 130nm to 200nm, critical dimension (CD) difference between two neighboring spaces was varied and it was assumed that micro loading effect was occurred in Qz etching. The linearity was guaranteed to dense L/S of 110nm and isolated line of 90nm, and Iso-Dense bias was controlled within 15nm. The 60nm and 70nm isolated lines of PE-PSM ware defined with good process windows in the case of OA_X size(X-direction size of Cr open area) of 0.5 ?m. The 55nm isolated line was also defined. The pattern shift of isolated lines was occurred with 4~7nm as phase of mask was varies within 190 ~ 200 ° . Though the alt-PSM with high numerical aperture (NA) for ArF lithography was strong candidates for sub-1 OOnm lithography of memory device, the issues of mask fabrication such as tighter phase control and minimizing etch loading effect would be big obstacles. On the contrary, there were many possibilities of sub-100nm patterning in PE-PSM with good process windows, however tighter control of pattern shift due to phase error must be studied intensively.