Weimin Wu

A new congestion-driven placement algorithm based on cell inflation

In this paper, we describe a new congestion-driven placement based on cell inflation. In our approach, we have used the method of probability- estimation to evaluate the routing of nets. We also take use of the strategy of cell inflation to eliminate the routing congestion. Further reduction in congestion is obtained by the scheme of cell moving. We have tested our algorithm on a set of sample circuits from American industry and the results obtained have shown great improvement of routability.

Congestion driven incremental placement algorithm for standard cell layout

Congestion minimization is the least understood in placement objectives, however, it models routability most accurately. In this paper, a new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion. Congestion estimation is based on a new routing model and a more accurate cost function. An integer linear programming (ILP) problem is formulated to determine cell flow direction and avoid the conflictions between adjacent congestion areas. Experimental results show that the algorithm can considerably reduce routing congestion and preserve the performance of the initial placement with high speed.

EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure

This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which is a unified procedure combining Boolean logic and arithmetic operations. A hybrid two- literal-watching scheme and interval reasoning based on RTL predicates are used as the powerful hybrid constraint propagation strategies. Conflict-based learning is also implemented as another important technique to enhance efficiency. Comparisons with a state-of-the-art RTL SAT solver, a SMT solver and an ILP solver show that EHSAT outperforms these solvers for RTL satisfiability problems.

Incremental placement algorithm for standard-cell layout

To satisfy timing constraints or complete clock net routing, it is sometimes necessary to make local modifications to circuits after placement. Redoing the time-consuming process of placement after each of these changes is no longer affordable. In this paper, we present a new algorithm W-ECOP to effect incremental changes on a standard cell layout automatically. This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do. Our method tries to minimize the adjustment on the initial placement and optimize the wirelength. Testing of W-ECOP on a group of practical test cases shows our algorithm can successfully accomplish incremental placement, with good quality and high speed.

FaSa: a fast and stable quadratic placement algorithm

Placement is a critical step in VLSI design because it dominates overall speed and quality of design flow. In this paper, a new fast and stable placement algorithm called FaSa is proposed. It uses quadratic programming model and Lagrange multiplier method to solve placement problems. And an incremental LU factorization method is used to solve equations for speeding up. The experimental results show that FaSa is very stable, much faster than previous algorithms and its total wire length is comparable with other algorithms.

Combining clustering and partitioning in quadratic placement

Because of the computation complexity of large circuits, the quadratic placement (Q-Place) cannot solve the placement problem fast enough without any preprocessing. In this paper, a method of combining the MFFC clustering and hMETIS partitioning based quadratic placement algorithm is proposed. Experimental results show it can gain good results but consume long running time. In order to cut down the running time, an improved MFFC clustering method (IMFFC) based Q-place algorithm is proposed in this paper. Comparing with the combining clustering and partitioning based method, it is much fast but with a little increase in total wire length.

A path-based timing-driven quadratic placement algorithm

This paper presents a path-based timing-driven quadratic placement algorithm. The delay of the path acts as the timing constraints. In the global optimization step, it tries to satisfy the timing constraints. In the partition step, it tries to decrease the cut number of critical paths. It has some special skills, such as decrease the delay on the longest path, pad assign, to decrease the delay further. Results show this algorithm can make the timing behavior improve more than 20%.

CEP: a clock-driven ECO placement algorithm for standard-cell layout

Incremental placement or ECO (engineer change order) placement is a new field in VLSI layout to meet the demand of high performance design. In this paper, a novel clock-driven ECO placement algorithm, CEP, is presented for standard cell layout design. It considers clock skew information in the placement stage, modifies the positions of cells locally to make better preparation for the clock routing. Experimental results show that CEP can improve the skew bounds distribution evidently, with little influence on other performance aspects.

The selection and creation of the rules in rules-based optical proximity correction

Considering the efficiency and veracity of rules-based OPC applied to recent large-scale layout, we firstly point out the importance of the selection and creation of rules in rules-based OPC. Our discussion addresses the crucial factors in selecting and creating rules as well as how we select and create more concise and practical rules-base. Based on our ideas we suggest four primary rules and as a result we show some rule data in table. The automatic construction of the rules-base called OPCL is an important part of the whole rules-based OPC software.

Standard-cell based data-path placement utilizing regularity

As more and more functions and operations are integrated into system-on-a-chip (SOC), data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design. But the traditional placement tool cannot obtain satisfied result of data-path circuit because it has no knowledge of the data-path bit-slice structure and the parallel constraint. In this paper, an algorithm named DPP will be addressed to handle the standard-cell based data-path placement. It exploits the signal flow of circuit to generate the structure regularity of cells. Then, it converts the bit-slice structure to parallel constraints and partition policy so as to enable Q-Place algorithm on the placement. The design flow and the main algorithms will be introduced. Finally, the paper will discuss the satisfied experimental result of the tool compared with the Cadence placement tool SE.As more and more functions and operations are integrated into system-on-a-chip (SOC), data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design. But the traditional placement tool cannot obtain satisfied result of data-path circuit because it has no knowledge of the data-path bit-slice structure and the parallel constraint. In this paper, an algorithm named DPP will be addressed to handle the standard-cell based data-path placement. It exploits the signal flow of circuit to generate the structure regularity of cells. Then, it converts the bit-slice structure to parallel constraints and partition policy so as to enable Q-Place algorithm on the placement. The design flow and the main algorithms will be introduced. Finally, the paper will discuss the satisfied experimental result of the tool compared with the Cadence placement tool SE.